summaryrefslogtreecommitdiff
path: root/doc/README.RPXlite
blob: 0aa4d11303bdad2801211dacd0eddc7dfb7ddbd6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
# Porting U-Boot onto RPXlite board
# Written by Yoo. Jonghoon
# E-Mail : yooth@ipone.co.kr
# IP ONE Inc.

# Since 2001. 1. 29

# Shell : bash
# Cross-compile tools : Montavista Hardhat
# Debugging tools : Windriver VisionProbe (PowerPC BDM)
# ppcboot ver. : ppcboot-0.8.1

###############################################################
#	1. Hardware setting
###############################################################

1.1. Board, BDM settings
	Install board, BDM, connect each other

1.2. Save Register value
	Boot with board-on monitor program and save the
	register values with BDM.

1.3. Configure flash programmer
	Check flash memory area in the memory map.
	0xFFC00000 - 0xFFFFFFFF

	Boot monitor program is at
	0xFFF00000

	You can program on-board flash memory with VisionClick
	flash programmer. Set the target flash device as:

	29DL800B

	(?) The flash memory device in the board *is* 29LV800B,
		but I cannot program it with '29LV800B' option.
		(in VisionClick flash programming tools)
		I don't know why...

1.4. Save boot monitor program *IMPORTANT*
	Upload boot monitor program from board to file.
	boot monitor program starts at 0xFFF00000

1.5. Test flash memory programming
	Try to erase boot program in the flash memory,
	and re-write them.
	*WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE
		BEFORE ERASING FLASH

###############################################################
#	2. U-Boot setting
###############################################################

2.1. Download U-Boot tarball at
	ftp://ftp.denx.de
	(The latest version is ppcboot-0.8.1.tar.bz2)

	To extract the archive use the following syntax :
	> bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf -

2.2. Add the following lines in '.profile'
	export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin

2.3. Make board specific config, for example:
	> cd ppcboot-0.8.1
	> make TQM860L_config

	Now we can build ppcboot bin files.
	After make all, you must see these files in your
	ppcboot root directory.

	ppcboot
	ppcboot.bin
	ppcboot.srec
	ppcboot.map

2.4. Make your own board directory into the
	ppcboot-0.8.1/board
	and make your board-specific files here.

	For exmanple, tqm8xx files are composed of
	.depend : Nothing
	Makefile : To make config file
	config.mk : Sets base address
	flash.c : Flash memory control files
	ppcboot.lds : linker(ld) script? (I don't know this yet)
	tqm8xx.c : DRAM control and board check routines

	And, add your board config lines in the
	ppcboot-0.8.1/Makefile

	Finally, add config_(your board).h file in the
	ppcboot-0.8.1/include/

	I've made board/rpxlite directory, and just copied
	tqm8xx settings for now.

	Rebuild ppcboot for rpxlite board:
	> make rpxlite_config
	> make

###############################################################
#	3. U-Boot porting
###############################################################

3.1. My RPXlite files are based on tqm8xx board files.
	> cd board
	> cp -r tqm8xx RPXLITE
	> cd RPXLITE
	> mv tqm8xx.c RPXLITE.c
	> cd ../../include
	> cp config_tqm8xx.h config_RPXLITE.h

3.2. Modified files are:
	board/RPXLITE/RPXLITE.c		/* DRAM-related routines */
	board/RPXLITE/flash.c		/* flash-related routines */
	board/RPXLITE/config.mk		/* set text base address */
	arch/ppc/cpu/mpc8xx/serial.c			/* board specific register setting */
	include/config_RPXLITE.h	/* board specific registers */

	See 'reg_config.txt' for register values in detail.

###############################################################
#	4. Running Linux
###############################################################


###############################################################
#	Misc Information
###############################################################

mem_config.txt:
===============

Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device
manufacturer id : 01     (AMD)
device id       : 5B     (AM29LV800B)
size            : 4Mbyte
sector #        : 19

Sector information :

number   start addr.     size
00       FFC0_0000       64
01       FFC1_0000       32
02       FFC1_8000       32
03       FFC2_0000       128
04       FFC4_0000       256
05       FFC8_0000       256
06       FFCC_0000       256
07       FFD0_0000       256
08       FFD4_0000       256
09       FFD8_0000       256
10       FFDC_0000       256
11       FFE0_0000       256
12       FFE4_0000       256
13       FFE8_0000       256
14       FFEC_0000       256
15       FFF0_0000       256
16       FFF4_0000       256
17       FFF8_0000       256
18       FFFC_0000       256


reg_config.txt:
===============


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	SIU (System Interface Unit) */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */


/*### IMMR */
/*### Internal Memory Map Register */
/*### Chap. 11.4.1 */

	ISB		= 0xFA20		/* Set the Immap base = 0xFA20 0000 */
	PARTNUM = 0x21
	MASKNUM = 0x00

	=> 0xFA20 2100

---------------------------------------------------------------------

/*### SIUMCR */
/*### SIU Module Configuration Register */
/*### Chap. 11.4.2 */
/*### Offset : 0x0000 0000 */

	EARB	= 0
	EARP	= 0
	DSHW	= 0
	DBGC	= 0
	DBPC	= 0
	FRC		= 0
	DLK		= 0
	OPAR	= 0
	PNCS	= 0
	DPC		= 0
	MPRE	= 0
	MLRC	= 10		/* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */
	AEME	= 0
	SEME	= 0
	BSC		= 0
	GB5E	= 0
	B2DD	= 0
	B3DD	= 0

	=> 0x0000 0800

---------------------------------------------------------------------

/*### SYPCR */
/*### System Protection Control Register */
/*### Chap. 11.4.3 */
/*### Offset : 0x0000 0004 */

	SWTC	= 0xFFFF	/* SW watchdog timer count = 0xFFFF */
	BMT		= 0x06		/* BUS monitoring timing */
	BME		= 1			/* BUS monitor enable */
	SWF		= 1
	SWE		= 0			/* SW watchdog disable */
	SWRI	= 0
	SWP		= 1

	=> 0xFFFF 0689

---------------------------------------------------------------------

/*### TESR */
/*### Transfer Error Status Register */
/*### Chap. 11.4.4 */
/*### Offset : 0x0000 0020 */

	IEXT	= 0
	ITMT	= 0
	IPB		= 0000
	DEXT	= 0
	DTMT	= 0
	DPB		= 0000

	=> 0x0000 0000

---------------------------------------------------------------------

/*### SIPEND */
/*### SIU Interrupt Pending Register */
/*### Chap. 11.5.4.1 */
/*### Offset : 0x0000 0010 */

	IRQ0~IRQ7 = 0
	LVL0~LVL7 = 0

	=> 0x0000 0000

---------------------------------------------------------------------

/*### SIMASK */
/*### SIU Interrupt Mask Register */
/*### Chap. 11.5.4.2 */
/*### Offset : 0x0000 0014 */

	IRM0~IRM7 = 0		/* Mask all interrupts */
	LVL0~LVL7 = 0

	=> 0x0000 0000

---------------------------------------------------------------------

/*### SIEL */
/*### SIU Interrupt Edge/Level Register */
/*### Chap. 11.5.4.3 */
/*### Offset : 0x0000 0018 */

	ED0~ED7 = 0			/* Low level triggered */
	WMn0~WMn7 = 0		/* Not allowed to exit from low-power mode */

	=> 0x0000 0000

---------------------------------------------------------------------

/*### SIVEC */
/*### SIU Interrupt Vector Register */
/*### Chap. 11.5.4.4 */
/*### Offset : 0x0000 001C */

	INTC = 3C		/* The lowest interrupt is pending..(?) */

	=> 0x3C00 0000

---------------------------------------------------------------------

/*### SWSR */
/*### Software Service Register */
/*### Chap. 11.7.1 */
/*### Offset : 0x0000 001E */

	SEQ = 0

	=> 0x0000

---------------------------------------------------------------------

/*### SDCR */
/*### SDMA Configuration Register */
/*### Chap. 20.2.1 */
/*### Offset : 0x0000 0032 */

	FRZ = 0
	RAID = 01	/* Priority level 5 (BR5) (normal operation) */

	=> 0x0000 0001


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	UPMA (User Programmable Machine A) */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */

/*### Chap. 16.6.4.1 */
/*### Offset = 0x0000 017c */

	T0  = CFFF CC24		/* Single Read */
	T1  = 0FFF CC04
	T2  = 0CAF CC04
	T3  = 03AF CC08
	T4  = 3FBF CC27		/* last */
	T5  = FFFF CC25
	T6  = FFFF CC25
	T7  = FFFF CC25
	T8  = CFFF CC24		/* Burst Read */
	T9  = 0FFF CC04
	T10 = 0CAF CC84
	T11 = 03AF CC88
	T12 = 3FBF CC27		/* last */
	T13 = FFFF CC25
	T14 = FFFF CC25
	T15 = FFFF CC25
	T16 = FFFF CC25
	T17 = FFFF CC25
	T18 = FFFF CC25
	T19 = FFFF CC25
	T20 = FFFF CC25
	T21 = FFFF CC25
	T22 = FFFF CC25
	T23 = FFFF CC25
	T24 = CFFF CC24		/* Single Write */
	T25 = 0FFF CC04
	T26 = 0CFF CC04
	T27 = 03FF CC00
	T28 = 3FFF CC27		/* last */
	T29 = FFFF CC25
	T30 = FFFF CC25
	T31 = FFFF CC25
	T32 = CFFF CC24		/* Burst Write */
	T33 = 0FFF CC04
	T34 = 0CFF CC80
	T35 = 03FF CC8C
	T36 = 0CFF CC00
	T37 = 33FF CC27		/* last */
	T38 = FFFF CC25
	T39 = FFFF CC25
	T40 = FFFF CC25
	T41 = FFFF CC25
	T42 = FFFF CC25
	T43 = FFFF CC25
	T44 = FFFF CC25
	T45 = FFFF CC25
	T46 = FFFF CC25
	T47 = FFFF CC25
	T48 = C0FF CC24		/* Refresh */
	T49 = 03FF CC24
	T50 = 0FFF CC24
	T51 = 0FFF CC24
	T52 = 3FFF CC27		/* last */
	T53 = FFFF CC25
	T54 = FFFF CC25
	T55 = FFFF CC25
	T56 = FFFF CC25
	T57 = FFFF CC25
	T58 = FFFF CC25
	T59 = FFFF CC25
	T60 = FFFF CC25		/* Exception */
	T61 = FFFF CC25
	T62 = FFFF CC25
	T63 = FFFF CC25


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	UPMB */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------

/*### Chap. 16.6.4.1 */


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	MEMC */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------

/*### BR0 & OR0 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */
/*### Flash memory */

	BA   = 1111 1110 0000 0000 0	/* Base addr = 0xFE00 0000 */
	AT   = 000
	PS   = 00
	PARE = 0
	WP   = 0
	MS   = 0				/* GPCM */
	V    = 1				/* Valid */

	=> 0xFE00 0001

	AM            = 1111 1110 0000 0000 0	/* 32MBytes */
	ATM           = 000
	CSNT/SAM      = 0
	ACS/G5LA,G5LS = 00
	BIH           = 1			/* Burst inhibited */
	SCY           = 0100		/* cycle length = 4 */
	SETA          = 0
	TRLX          = 0
	EHTR          = 0

	=> 0xFE00 0140

/*### BR1 & OR1 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */
/*### SDRAM */

	BA   = 0000 0000 0000 0000 0	/* Base addr = 0x0000 0000 */
	AT   = 000
	PS   = 00
	PARE = 0
	WP   = 0
	MS   = 1				/* UPMA */
	V    = 1				/* Valid */

	=> 0x0000 0081

	AM            = 1111 1110 0000 0000	/* 32MBytes */
	ATM           = 000
	CSNT/SAM      = 1
	ACS/G5LA,G5LS = 11
	BIH           = 0
	SCY           = 0000		/* cycle length = 0 */
	SETA          = 0
	TRLX          = 0
	EHTR          = 0

	=> 0xFE00 0E00

/*### BR2 & OR2 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */

	BR2 & OR2 = 0x0000 0000		/* Not used */

/*### BR3 & OR3 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */
/*### BCSR */

	BA   = 1111 1010 0100 0000 0	/* Base addr = 0xFA40 0000 */
	AT   = 000
	PS   = 00
	PARE = 0
	WP   = 0
	MS   = 0				/* GPCM */
	V    = 1				/* Valid */

	=> 0xFA40 0001

	AM            = 1111 1111 0111 1111 1	/* (?) */
	ATM           = 000
	CSNT/SAM      = 1
	ACS/G5LA,G5LS = 00
	BIH           = 1			/* Burst inhibited */
	SCY           = 0001		/* cycle length = 1 */
	SETA          = 0
	TRLX          = 0

	=> 0xFF7F 8910

/*### BR4 & OR4 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */
/*### NVRAM & SRAM */

	BA   = 1111 1010 0000 0000 0	/* Base addr = 0xFA00 0000 */
	AT   = 000
	PS   = 01
	PARE = 0
	WP   = 0
	MS   = 0				/* GPCM */
	V    = 1				/* Valid */

	=> 0xFA00 0401

	AM            = 1111 1111 1111 1000 0	/* 8MByte */
	ATM           = 000
	CSNT/SAM      = 1
	ACS/G5LA,G5LS = 00
	BIH           = 1			/* Burst inhibited */
	SCY           = 0111		/* cycle length = 7 */
	SETA          = 0
	TRLX          = 0

	=> 0xFFF8 0970

/*### BR5 & OR5 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */

	BR5 & OR5 = 0x0000 0000		/* Not used */

/*### BR6 & OR6 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */

	BR6 & OR6 = 0x0000 0000		/* Not used */

/*### BR7 & OR7 */
/*### Base Registers & Option Registers */
/*### Chap. 16.4.1 & 16.4.2 */
/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */

	BR7 & OR7 = 0x0000 0000		/* Not used */

/*### MAR */
/*### Memory Address Register */
/*### Chap. 16.4.7 */
/*### Offset : 0x0000 0164 */

	MA = External memory address

/*### MCR */
/*### Memory Command Register */
/*### Chap. 16.4.5 */
/*### Offset : 0x0000 0168 */

	OP   = xx			/* Command op code */
	UM   = 1			/* Select UPMA */
	MB   = 001			/* Select CS1 */
	MCLF = xxxx			/* Loop times */
	MAD  = xx xxxx		/* Memory array index */

/*### MAMR */
/*### Machine A Mode Register */
/*### Chap. 16.4.4 */
/*### Offset : 0x0000 0170 */

	PTA = 0101 1000
	PTAE = 1			/* Periodic timer A enabled */
	AMA = 010
	DSA = 00
	G0CLA = 000
	GPLA4DIS = 1
	RLFA = 0100
	WLFA = 0011
	TLFA = 0000

	=> 0x58A0 1430

/*### MBMR */
/*### Machine B Mode Register */
/*### Chap. 16.4.4 */
/*### Offset : 0x0000 0174 */

	PTA = 0100 1110
	PTAE = 0			/* Periodic timer B disabled */
	AMA = 000
	DSA = 00
	G0CLA = 000
	GPLA4DIS = 1
	RLFA = 0000
	WLFA = 0000
	TLFA = 0000

	=> 0x4E00 1000

/*### MSTAT */
/*### Memory Status Register */
/*### Chap. 16.4.3 */
/*### Offset : 0x0000 0178 */

	PER0~PER7 = Parity error
	WPER      = Write protection error

	=> 0x0000

/*### MPTPR */
/*### Memory Periodic Timer Prescaler Register */
/*### Chap. 16.4.8 */
/*### Offset : 0x0000 017A */

	PTP = 0000 1000		/* Divide by 8 */

	=> 0x0800

/*### MDR */
/*### Memory Data Register */
/*### Chap. 16.4.6 */
/*### Offset : 0x0000 017C */

	MD = Memory data contains the RAM array word


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	TIMERS */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------

/*### TBREFx */
/*### Timebase Reference Registers */
/*### Chap. 11.9.2 */
/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */
/*### (Locked) */

	TBREFF0 = 0xFFFF FFFF
	TBREFF1 = 0xFFFF FFFF

---------------------------------------------------------------------

/*### TBSCR */
/*### Timebase Status and Control Registers */
/*### Chap. 11.9.3 */
/*### Offset : 0x0000 0200 */
/*### (Locked) */

	TBIRQ = 00000000
	REF0  = 0
	REF1  = 0
	REFE0 = 0			/* Reference interrupt disable */
	REFE1 = 0
	TBF   = 1
	TBE   = 1			/* Timebase enable */

	=> 0x0003

---------------------------------------------------------------------

/*### RTCSC */
/*### Real-Time Clock Status and Control Registers */
/*### Chap. 11.10.1 */
/*### Offset : 0x0000 0220 */
/*### (Locked) */

	RTCIRQ = 00000000
	SEC = 1
	ALR = 0
	38K = 0				/* PITRTCLK is driven by 32.768KHz */
	SIE = 0
	ALE = 0
	RTF = 0
	RTE = 1				/* Real-Time clock enabled */

	=> 0x0081

---------------------------------------------------------------------

/*### RTC */
/*### Real-Time Clock Registers */
/*### Chap. 11.10.2 */
/*### Offset : 0x0000 0224 */
/*### (Locked) */

	RTC = Real time clock measured in second

---------------------------------------------------------------------

/*### RTCAL */
/*### Real-Time Clock Alarm Registers */
/*### Chap. 11.10.3 */
/*### Offset : 0x0000 022C */
/*### (Locked) */

	ALARM = 0xFFFF FFFF

---------------------------------------------------------------------

/*### RTSEC */
/*### Real-Time Clock Alarm Second Registers */
/*### Chap. 11.10.4 */
/*### Offset : 0x0000 0228 */
/*### (Locked) */

	COUNTER = Counter bits(fraction of a second)

---------------------------------------------------------------------

/*### PISCR */
/*### Periodic Interrupt Status and Control Register */
/*### Chap. 11.11.1 */
/*### Offset : 0x0000 0240 */
/*### (Locked) */

	PIRQ = 0
	PS   = 0		/* Write 1 to clear */
	PIE  = 0
	PITF = 1
	PTE  = 0		/* PIT disabled */

---------------------------------------------------------------------

/*### PITC */
/*### PIT Count Register */
/*### Chap. 11.11.2 */
/*### Offset : 0x0000 0244 */
/*### (Locked) */

	PITC = PIT count

---------------------------------------------------------------------

/*### PITR */
/*### PIT Register */
/*### Chap. 11.11.3 */
/*### Offset : 0x0000 0248 */
/*### (Locked) */

	PIT = PIT count		/* Read only */


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	CLOCKS */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------


---------------------------------------------------------------------

/*### SCCR */
/*### System Clock and Reset Control Register */
/*### Chap. 15.6.1 */
/*### Offset : 0x0000 0280 */
/*### (Locked) */

	COM    = 11		/* Clock output disabled */
	TBS    = 1		/* Timebase frequency source is GCLK2 divided by 16 */
	RTDIV  = 0		/* The clock is divided by 4 */
	RTSEL  = 0		/* OSCM(Crystal oscillator) is selected */
	CRQEN  = 0
	PRQEN  = 0
	EBDF   = 00		/* CLKOUT is GCLK2 divided by 1 */
	DFSYNC = 00		/* Divided by 1 (normal operation) */
	DFBRG  = 00		/* Divided by 1 (normal operation) */
	DFNL   = 000
	DFNH   = 000

	=> 0x6200 0000

---------------------------------------------------------------------

/*### PLPRCR */
/*### PLL, Low-Power, and Reset Control Register */
/*### Chap. 15.6.2 */
/*### Offset : 0x0000 0284 */
/*### (Locked) */

	MF    = 0x005	/* 48MHz (?) (  = 8MHz * (MF+1) ) */
	SPLSS = 0
	TEXPS = 0
	TMIST = 0
	CSRC  = 0		/* The general system clock is generated by the DFNH field */
	LPM   = 00		/* Normal high/normal low mode */
	CSR   = 0
	LOLRE = 0
	FIOPD = 0

	=> 0x0050 0000

---------------------------------------------------------------------

/*### RSR */
/*### Reset Status Register */
/*### Chap. 12.2 */
/*### Offset : 0x0000 0288 */
/*### (Locked) */

	EHRS  = External hard reset
	ESRS  = External soft reset
	LLRS  = Loss-of-lock reset
	SWRS  = Software watchdog reset
	CSRS  = Check stop reset
	DBHRS = Debug port hard reset
	DBSRS = Debug port soft reset
	JTRS  = JTAG reset


/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
/*	DMA */
/* */
/*------------------------------------------------------------------- */
/*------------------------------------------------------------------- */
---------------------------------------------------------------------

/*### SDSR */
/*### SDMA Status Register */
/*### Chap. 20.2.2 */
/*### Offset : 0x0000 0908 */

	SBER = 0	/* SDMA channel bus error */
	DSP2 = 0	/* DSP chain2 (Tx) interrupt */
	DSP1 = 0	/* DSP chain1 (Rx) interrupt */

	=> 0x00

/*### SDMR */
/*### SDMA Mask Register */
/*### Chap. 20.2.3 */
/*### Offset : 0x0000 090C */

	SBER = 0
	DSP2 = 0
	DSP1 = 0	/* All interrupts are masked */

	=> 0x00

/*### SDAR */
/*### SDMA Address Register */
/*### Chap. 20.2.4 */
/*### Offset : 0x0000 0904 */

	AR = 0xxxxx xxxx	/* current system address */

	=> 0xFA20 23AC

/*### IDSRx */
/*### IDMA Status Register */
/*### Chap. 20.3.3.2 */
/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */

	AD   = 0
	DONE = 0
	OB   = 0

	=> 0x00

/*### IDMRx */
/*### IDMA Mask Register */
/*### Chap. 20.3.3.3 */
/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */

	AD   = 0
	DONE = 0
	OB   = 0