summaryrefslogtreecommitdiff
path: root/board/freescale/bsc9132qds/bsc9132qds.c
blob: ddc9d0a16a4fb8f63a049f0d4a297bb753494b7f (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
#include <asm/fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>

#ifdef CONFIG_PCI
#include <pci.h>
#include <asm/fsl_pci.h>
#endif

#include "../common/qixis.h"
DECLARE_GLOBAL_DATA_PTR;


int board_early_init_f(void)
{
	struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR;

	setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);

	return 0;
}

void board_config_serdes_mux(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 pordevsr = in_be32(&gur->pordevsr);
	u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
				MPC85xx_PORDEVSR_IO_SEL_SHIFT;

	switch (srds_cfg) {
	/* PEX(1) PEX(2) CPRI 2 CPRI 1 */
	case  1:
	case  2:
	case  3:
	case  4:
	case  5:
	case 22:
	case 23:
	case 24:
	case 25:
	case 26:
		QIXIS_WRITE_I2C(brdcfg[4], 0x03);
		break;

	/* PEX(1) PEX(2) SGMII1 CPRI 1 */
	case  6:
	case  7:
	case  8:
	case  9:
	case 10:
	case 27:
	case 28:
	case 29:
	case 30:
	case 31:
		QIXIS_WRITE_I2C(brdcfg[4], 0x01);
		break;

	/* PEX(1) PEX(2) SGMII1 SGMII2 */
	case 11:
	case 32:
		QIXIS_WRITE_I2C(brdcfg[4], 0x00);
		break;

	/* PEX(1) SGMII2 CPRI 2 CPRI 1 */
	case 12:
	case 13:
	case 14:
	case 15:
	case 16:
	case 33:
	case 34:
	case 35:
	case 36:
	case 37:
		QIXIS_WRITE_I2C(brdcfg[4], 0x07);
		break;

	/* PEX(1) SGMII2 SGMII1 CPRI 1 */
	case 17:
	case 18:
	case 19:
	case 20:
	case 21:
	case 38:
	case 39:
	case 40:
	case 41:
	case 42:
		QIXIS_WRITE_I2C(brdcfg[4], 0x05);
		break;

	/* SGMII1 SGMII2 CPRI 2 CPRI 1 */
	case 43:
	case 44:
	case 45:
	case 46:
	case 47:
		QIXIS_WRITE_I2C(brdcfg[4], 0x0F);
		break;


	default:
		break;
	}
}

int board_early_init_r(void)
{
#ifndef CONFIG_SYS_NO_FLASH
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	/* invalidate existing TLB entry for flash */
	disable_tlb(flash_esel);

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel, BOOKE_PAGESZ_64M, 1);

	set_tlb(1, flashbase + 0x4000000,
			CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
			0, flash_esel+1, BOOKE_PAGESZ_64M, 1);
#endif
	board_config_serdes_mux();
	return 0;
}

#ifdef CONFIG_PCI
void pci_init_board(void)
{
	fsl_pcie_init_board(0);
}
#endif /* ifdef CONFIG_PCI */

int checkboard(void)
{
	struct cpu_type *cpu;
	u8 sw;

	cpu = gd->arch.cpu;
	printf("Board: %sQDS\n", cpu->name);

	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n",
	QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));

	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	printf("IFC chip select:");
	switch (sw) {
	case 0:
		printf("NOR\n");
		break;
	case 2:
		printf("Promjet\n");
		break;
	case 4:
		printf("NAND\n");
		break;
	default:
		printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
		break;
	}

	return 0;
}

#ifdef CONFIG_TSEC_ENET
int board_eth_init(bd_t *bis)
{
	struct fsl_pq_mdio_info mdio_info;
	struct tsec_info_struct tsec_info[4];
	int num = 0;

#ifdef CONFIG_TSEC1
	SET_STD_TSEC_INFO(tsec_info[num], 1);
	num++;

#endif

#ifdef CONFIG_TSEC2
	SET_STD_TSEC_INFO(tsec_info[num], 2);
	num++;
#endif

	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
	mdio_info.name = DEFAULT_MII_NAME;

	fsl_pq_mdio_init(bis, &mdio_info);
	tsec_eth_init(bis, tsec_info, num);

	#ifdef CONFIG_PCI
	pci_eth_init(bis);
	#endif

	return 0;
}
#endif

#define USBMUX_SEL_MASK		0xc0
#define USBMUX_SEL_UART2	0xc0
#define USBMUX_SEL_USB		0x40
#define SPIMUX_SEL_UART3	0x80
#define GPS_MUX_SEL_GPS		0x40

#define TSEC_1588_CLKIN_MASK	0x03
#define CON_XCVR_REF_CLK	0x00

int misc_init_r(void)
{
	u8 val;
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 porbmsr = in_be32(&gur->porbmsr);
	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;

	/*Configure 1588 clock-in source from RF Card*/
	val = QIXIS_READ_I2C(brdcfg[5]);
	QIXIS_WRITE_I2C(brdcfg[5],
		(val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK);

	if (hwconfig("uart2") && hwconfig("usb1")) {
		printf("UART2 and USB cannot work together on the board\n");
		printf("Remove one from hwconfig and reset\n");
	} else {
		if (hwconfig("uart2")) {
			val = QIXIS_READ_I2C(brdcfg[5]);
			QIXIS_WRITE_I2C(brdcfg[5],
				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2);
			clrbits_be32(&gur->pmuxcr3,
						MPC85xx_PMUXCR3_USB_SEL_MASK);
			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL);
		} else {
			/* By default USB should be selected.
			* Programming FPGA to select USB. */
			val = QIXIS_READ_I2C(brdcfg[5]);
			QIXIS_WRITE_I2C(brdcfg[5],
				(val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB);
		}

	}

	if (hwconfig("sim")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SPI) {

			val = QIXIS_READ_I2C(brdcfg[3]);
			QIXIS_WRITE_I2C(brdcfg[3], val|0x10);
			clrbits_be32(&gur->pmuxcr,
				MPC85xx_PMUXCR0_SIM_SEL_MASK);
			setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL);
		}
	}

	if (hwconfig("uart3")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SDHC) {

			/* UART3 and SPI1 (Flashes) are muxed together */
			val = QIXIS_READ_I2C(brdcfg[3]);
			QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3));
			clrbits_be32(&gur->pmuxcr3,
						MPC85xx_PMUXCR3_UART3_SEL_MASK);
			setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL);

			/* MUX to select UART3 connection to J24 header
			 * or to GPS */
			val = QIXIS_READ_I2C(brdcfg[6]);
			if (hwconfig("gps"))
				QIXIS_WRITE_I2C(brdcfg[6],
						(val | GPS_MUX_SEL_GPS));
			else
				QIXIS_WRITE_I2C(brdcfg[6],
						(val & ~(GPS_MUX_SEL_GPS)));
		}
	}
	return 0;
}

void fdt_del_node_compat(void *blob, const char *compatible)
{
	int err;
	int off = fdt_node_offset_by_compatible(blob, -1, compatible);
	if (off < 0) {
		printf("WARNING: could not find compatible node %s: %s.\n",
			compatible, fdt_strerror(off));
		return;
	}
	err = fdt_del_node(blob, off);
	if (err < 0) {
		printf("WARNING: could not remove %s: %s.\n",
			compatible, fdt_strerror(err));
	}
}

#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	#if defined(CONFIG_PCI)
	FT_FSL_PCI_SETUP;
	#endif

	fdt_fixup_memory(blob, (u64)base, (u64)size);

	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 porbmsr = in_be32(&gur->porbmsr);
	u32 romloc = (porbmsr >> MPC85xx_PORBMSR_ROMLOC_SHIFT) & 0xf;

	if (!(hwconfig("uart2") && hwconfig("usb1"))) {
		/* If uart2 is there in hwconfig remove usb node from
		 *  device tree */

		if (hwconfig("uart2")) {
			/* remove dts usb node */
			fdt_del_node_compat(blob, "fsl-usb2-dr");
		} else {
			fdt_fixup_dr_usb(blob, bd);
			fdt_del_node_and_alias(blob, "serial2");
		}
	}

	if (hwconfig("uart3")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SDHC)
			/* Delete SPI node from the device tree */
				fdt_del_node_and_alias(blob, "spi1");
	} else
		fdt_del_node_and_alias(blob, "serial3");

	if (hwconfig("sim")) {
		if (romloc == PORBMSR_ROMLOC_NAND_2K ||
			romloc == PORBMSR_ROMLOC_NOR ||
			romloc == PORBMSR_ROMLOC_SPI) {

			/* remove dts sdhc node */
			fdt_del_node_compat(blob, "fsl,esdhc");
		} else if (romloc == PORBMSR_ROMLOC_SDHC) {

			/* remove dts sim node */
			fdt_del_node_compat(blob, "fsl,sim-v1.0");
			printf("SIM & SDHC can't work together on the board");
			printf("\nRemove sim from hwconfig and reset\n");
		}
	}
}
#endif