summaryrefslogtreecommitdiff
path: root/arch/blackfin/include/asm/mach-bf548/ADSP-EDN-BF544-extended_cdef.h
blob: 4c0fdf52bffaffc0921ae716909df066f91996ce (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318
3319
3320
3321
3322
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335
3336
3337
3338
3339
3340
3341
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375
3376
3377
3378
3379
3380
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425
3426
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562
3563
3564
3565
3566
3567
3568
3569
3570
3571
3572
3573
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583
3584
3585
3586
3587
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631
3632
3633
3634
3635
3636
3637
3638
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648
3649
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673
3674
3675
3676
3677
3678
3679
3680
3681
3682
3683
3684
3685
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702
3703
3704
3705
3706
3707
3708
3709
3710
3711
3712
3713
3714
3715
3716
3717
3718
3719
3720
3721
3722
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854
3855
3856
3857
3858
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883
3884
3885
3886
3887
3888
3889
3890
3891
3892
3893
3894
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907
3908
3909
3910
3911
3912
3913
3914
3915
3916
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073
4074
4075
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086
4087
4088
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104
4105
4106
4107
4108
4109
4110
4111
4112
4113
4114
4115
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135
4136
4137
4138
4139
4140
4141
4142
4143
4144
4145
4146
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239
4240
4241
4242
4243
4244
4245
4246
4247
4248
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265
4266
4267
4268
4269
4270
4271
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319
4320
4321
4322
4323
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350
4351
4352
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362
4363
4364
4365
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384
4385
4386
4387
4388
4389
4390
4391
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401
4402
4403
4404
4405
4406
4407
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428
4429
4430
4431
4432
4433
4434
4435
4436
4437
4438
4439
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483
4484
4485
4486
4487
4488
4489
4490
4491
4492
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514
4515
4516
4517
4518
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535
4536
4537
4538
4539
4540
4541
4542
4543
4544
4545
4546
4547
4548
4549
4550
4551
4552
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567
4568
4569
4570
4571
4572
4573
4574
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626
4627
4628
4629
4630
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653
4654
4655
4656
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693
4694
4695
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727
4728
4729
4730
4731
4732
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744
4745
4746
4747
4748
4749
4750
4751
4752
4753
4754
4755
4756
4757
4758
4759
4760
4761
4762
4763
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825
4826
4827
4828
4829
4830
4831
4832
4833
4834
4835
4836
4837
4838
4839
4840
4841
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868
4869
4870
4871
4872
4873
4874
4875
4876
4877
4878
4879
4880
4881
4882
4883
4884
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912
4913
4914
4915
4916
4917
4918
4919
4920
4921
4922
4923
4924
4925
4926
4927
4928
4929
4930
4931
4932
4933
4934
4935
4936
4937
4938
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957
4958
4959
4960
4961
4962
4963
4964
4965
4966
4967
4968
4969
4970
4971
4972
/* DO NOT EDIT THIS FILE
 * Automatically generated by generate-cdef-headers.xsl
 * DO NOT EDIT THIS FILE
 */

#ifndef __BFIN_CDEF_ADSP_EDN_BF544_extended__
#define __BFIN_CDEF_ADSP_EDN_BF544_extended__

#define pSIC_IMASK0                    ((uint32_t volatile *)SIC_IMASK0) /* System Interrupt Mask Register 0 */
#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
#define pSIC_IMASK1                    ((uint32_t volatile *)SIC_IMASK1) /* System Interrupt Mask Register 1 */
#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
#define pSIC_IMASK2                    ((uint32_t volatile *)SIC_IMASK2) /* System Interrupt Mask Register 2 */
#define bfin_read_SIC_IMASK2()         bfin_read32(SIC_IMASK2)
#define bfin_write_SIC_IMASK2(val)     bfin_write32(SIC_IMASK2, val)
#define pSIC_ISR0                      ((uint32_t volatile *)SIC_ISR0) /* System Interrupt Status Register 0 */
#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
#define pSIC_ISR1                      ((uint32_t volatile *)SIC_ISR1) /* System Interrupt Status Register 1 */
#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
#define pSIC_ISR2                      ((uint32_t volatile *)SIC_ISR2) /* System Interrupt Status Register 2 */
#define bfin_read_SIC_ISR2()           bfin_read32(SIC_ISR2)
#define bfin_write_SIC_ISR2(val)       bfin_write32(SIC_ISR2, val)
#define pSIC_IWR0                      ((uint32_t volatile *)SIC_IWR0) /* System Interrupt Wakeup Register 0 */
#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
#define pSIC_IWR1                      ((uint32_t volatile *)SIC_IWR1) /* System Interrupt Wakeup Register 1 */
#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
#define pSIC_IWR2                      ((uint32_t volatile *)SIC_IWR2) /* System Interrupt Wakeup Register 2 */
#define bfin_read_SIC_IWR2()           bfin_read32(SIC_IWR2)
#define bfin_write_SIC_IWR2(val)       bfin_write32(SIC_IWR2, val)
#define pSIC_IAR0                      ((uint32_t volatile *)SIC_IAR0) /* System Interrupt Assignment Register 0 */
#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
#define pSIC_IAR1                      ((uint32_t volatile *)SIC_IAR1) /* System Interrupt Assignment Register 1 */
#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
#define pSIC_IAR2                      ((uint32_t volatile *)SIC_IAR2) /* System Interrupt Assignment Register 2 */
#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
#define pSIC_IAR3                      ((uint32_t volatile *)SIC_IAR3) /* System Interrupt Assignment Register 3 */
#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
#define pSIC_IAR4                      ((uint32_t volatile *)SIC_IAR4) /* System Interrupt Assignment Register 4 */
#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
#define pSIC_IAR5                      ((uint32_t volatile *)SIC_IAR5) /* System Interrupt Assignment Register 5 */
#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
#define pSIC_IAR6                      ((uint32_t volatile *)SIC_IAR6) /* System Interrupt Assignment Register 6 */
#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
#define pSIC_IAR7                      ((uint32_t volatile *)SIC_IAR7) /* System Interrupt Assignment Register 7 */
#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
#define pSIC_IAR8                      ((uint32_t volatile *)SIC_IAR8) /* System Interrupt Assignment Register 8 */
#define bfin_read_SIC_IAR8()           bfin_read32(SIC_IAR8)
#define bfin_write_SIC_IAR8(val)       bfin_write32(SIC_IAR8, val)
#define pSIC_IAR9                      ((uint32_t volatile *)SIC_IAR9) /* System Interrupt Assignment Register 9 */
#define bfin_read_SIC_IAR9()           bfin_read32(SIC_IAR9)
#define bfin_write_SIC_IAR9(val)       bfin_write32(SIC_IAR9, val)
#define pSIC_IAR10                     ((uint32_t volatile *)SIC_IAR10) /* System Interrupt Assignment Register 10 */
#define bfin_read_SIC_IAR10()          bfin_read32(SIC_IAR10)
#define bfin_write_SIC_IAR10(val)      bfin_write32(SIC_IAR10, val)
#define pSIC_IAR11                     ((uint32_t volatile *)SIC_IAR11) /* System Interrupt Assignment Register 11 */
#define bfin_read_SIC_IAR11()          bfin_read32(SIC_IAR11)
#define bfin_write_SIC_IAR11(val)      bfin_write32(SIC_IAR11, val)
#define pDMAC0_TCPER                   ((uint16_t volatile *)DMAC0_TCPER) /* DMA Controller 0 Traffic Control Periods Register */
#define bfin_read_DMAC0_TCPER()        bfin_read16(DMAC0_TCPER)
#define bfin_write_DMAC0_TCPER(val)    bfin_write16(DMAC0_TCPER, val)
#define pDMAC0_TCCNT                   ((uint16_t volatile *)DMAC0_TCCNT) /* DMA Controller 0 Current Counts Register */
#define bfin_read_DMAC0_TCCNT()        bfin_read16(DMAC0_TCCNT)
#define bfin_write_DMAC0_TCCNT(val)    bfin_write16(DMAC0_TCCNT, val)
#define pDMAC1_TCPER                   ((uint16_t volatile *)DMAC1_TCPER) /* DMA Controller 1 Traffic Control Periods Register */
#define bfin_read_DMAC1_TCPER()        bfin_read16(DMAC1_TCPER)
#define bfin_write_DMAC1_TCPER(val)    bfin_write16(DMAC1_TCPER, val)
#define pDMAC1_TCCNT                   ((uint16_t volatile *)DMAC1_TCCNT) /* DMA Controller 1 Current Counts Register */
#define bfin_read_DMAC1_TCCNT()        bfin_read16(DMAC1_TCCNT)
#define bfin_write_DMAC1_TCCNT(val)    bfin_write16(DMAC1_TCCNT, val)
#define pDMAC1_PERIMUX                 ((uint16_t volatile *)DMAC1_PERIMUX) /* DMA Controller 1 Peripheral Multiplexer Register */
#define bfin_read_DMAC1_PERIMUX()      bfin_read16(DMAC1_PERIMUX)
#define bfin_write_DMAC1_PERIMUX(val)  bfin_write16(DMAC1_PERIMUX, val)
#define pDMA0_NEXT_DESC_PTR            ((void * volatile *)DMA0_NEXT_DESC_PTR) /* DMA Channel 0 Next Descriptor Pointer Register */
#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
#define pDMA0_START_ADDR               ((void * volatile *)DMA0_START_ADDR) /* DMA Channel 0 Start Address Register */
#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
#define pDMA0_CONFIG                   ((uint16_t volatile *)DMA0_CONFIG) /* DMA Channel 0 Configuration Register */
#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
#define pDMA0_X_COUNT                  ((uint16_t volatile *)DMA0_X_COUNT) /* DMA Channel 0 X Count Register */
#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
#define pDMA0_X_MODIFY                 ((uint16_t volatile *)DMA0_X_MODIFY) /* DMA Channel 0 X Modify Register */
#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
#define pDMA0_Y_COUNT                  ((uint16_t volatile *)DMA0_Y_COUNT) /* DMA Channel 0 Y Count Register */
#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
#define pDMA0_Y_MODIFY                 ((uint16_t volatile *)DMA0_Y_MODIFY) /* DMA Channel 0 Y Modify Register */
#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
#define pDMA0_CURR_DESC_PTR            ((void * volatile *)DMA0_CURR_DESC_PTR) /* DMA Channel 0 Current Descriptor Pointer Register */
#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
#define pDMA0_CURR_ADDR                ((void * volatile *)DMA0_CURR_ADDR) /* DMA Channel 0 Current Address Register */
#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
#define pDMA0_IRQ_STATUS               ((uint16_t volatile *)DMA0_IRQ_STATUS) /* DMA Channel 0 Interrupt/Status Register */
#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
#define pDMA0_PERIPHERAL_MAP           ((uint16_t volatile *)DMA0_PERIPHERAL_MAP) /* DMA Channel 0 Peripheral Map Register */
#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
#define pDMA0_CURR_X_COUNT             ((uint16_t volatile *)DMA0_CURR_X_COUNT) /* DMA Channel 0 Current X Count Register */
#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
#define pDMA0_CURR_Y_COUNT             ((uint16_t volatile *)DMA0_CURR_Y_COUNT) /* DMA Channel 0 Current Y Count Register */
#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
#define pDMA1_NEXT_DESC_PTR            ((void * volatile *)DMA1_NEXT_DESC_PTR) /* DMA Channel 1 Next Descriptor Pointer Register */
#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
#define pDMA1_START_ADDR               ((void * volatile *)DMA1_START_ADDR) /* DMA Channel 1 Start Address Register */
#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
#define pDMA1_CONFIG                   ((uint16_t volatile *)DMA1_CONFIG) /* DMA Channel 1 Configuration Register */
#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
#define pDMA1_X_COUNT                  ((uint16_t volatile *)DMA1_X_COUNT) /* DMA Channel 1 X Count Register */
#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
#define pDMA1_X_MODIFY                 ((uint16_t volatile *)DMA1_X_MODIFY) /* DMA Channel 1 X Modify Register */
#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
#define pDMA1_Y_COUNT                  ((uint16_t volatile *)DMA1_Y_COUNT) /* DMA Channel 1 Y Count Register */
#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
#define pDMA1_Y_MODIFY                 ((uint16_t volatile *)DMA1_Y_MODIFY) /* DMA Channel 1 Y Modify Register */
#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
#define pDMA1_CURR_DESC_PTR            ((void * volatile *)DMA1_CURR_DESC_PTR) /* DMA Channel 1 Current Descriptor Pointer Register */
#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
#define pDMA1_CURR_ADDR                ((void * volatile *)DMA1_CURR_ADDR) /* DMA Channel 1 Current Address Register */
#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
#define pDMA1_IRQ_STATUS               ((uint16_t volatile *)DMA1_IRQ_STATUS) /* DMA Channel 1 Interrupt/Status Register */
#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
#define pDMA1_PERIPHERAL_MAP           ((uint16_t volatile *)DMA1_PERIPHERAL_MAP) /* DMA Channel 1 Peripheral Map Register */
#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
#define pDMA1_CURR_X_COUNT             ((uint16_t volatile *)DMA1_CURR_X_COUNT) /* DMA Channel 1 Current X Count Register */
#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
#define pDMA1_CURR_Y_COUNT             ((uint16_t volatile *)DMA1_CURR_Y_COUNT) /* DMA Channel 1 Current Y Count Register */
#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
#define pDMA2_NEXT_DESC_PTR            ((void * volatile *)DMA2_NEXT_DESC_PTR) /* DMA Channel 2 Next Descriptor Pointer Register */
#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
#define pDMA2_START_ADDR               ((void * volatile *)DMA2_START_ADDR) /* DMA Channel 2 Start Address Register */
#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
#define pDMA2_CONFIG                   ((uint16_t volatile *)DMA2_CONFIG) /* DMA Channel 2 Configuration Register */
#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
#define pDMA2_X_COUNT                  ((uint16_t volatile *)DMA2_X_COUNT) /* DMA Channel 2 X Count Register */
#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
#define pDMA2_X_MODIFY                 ((uint16_t volatile *)DMA2_X_MODIFY) /* DMA Channel 2 X Modify Register */
#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
#define pDMA2_Y_COUNT                  ((uint16_t volatile *)DMA2_Y_COUNT) /* DMA Channel 2 Y Count Register */
#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
#define pDMA2_Y_MODIFY                 ((uint16_t volatile *)DMA2_Y_MODIFY) /* DMA Channel 2 Y Modify Register */
#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
#define pDMA2_CURR_DESC_PTR            ((void * volatile *)DMA2_CURR_DESC_PTR) /* DMA Channel 2 Current Descriptor Pointer Register */
#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
#define pDMA2_CURR_ADDR                ((void * volatile *)DMA2_CURR_ADDR) /* DMA Channel 2 Current Address Register */
#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
#define pDMA2_IRQ_STATUS               ((uint16_t volatile *)DMA2_IRQ_STATUS) /* DMA Channel 2 Interrupt/Status Register */
#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
#define pDMA2_PERIPHERAL_MAP           ((uint16_t volatile *)DMA2_PERIPHERAL_MAP) /* DMA Channel 2 Peripheral Map Register */
#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
#define pDMA2_CURR_X_COUNT             ((uint16_t volatile *)DMA2_CURR_X_COUNT) /* DMA Channel 2 Current X Count Register */
#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
#define pDMA2_CURR_Y_COUNT             ((uint16_t volatile *)DMA2_CURR_Y_COUNT) /* DMA Channel 2 Current Y Count Register */
#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
#define pDMA3_NEXT_DESC_PTR            ((void * volatile *)DMA3_NEXT_DESC_PTR) /* DMA Channel 3 Next Descriptor Pointer Register */
#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
#define pDMA3_START_ADDR               ((void * volatile *)DMA3_START_ADDR) /* DMA Channel 3 Start Address Register */
#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
#define pDMA3_CONFIG                   ((uint16_t volatile *)DMA3_CONFIG) /* DMA Channel 3 Configuration Register */
#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
#define pDMA3_X_COUNT                  ((uint16_t volatile *)DMA3_X_COUNT) /* DMA Channel 3 X Count Register */
#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
#define pDMA3_X_MODIFY                 ((uint16_t volatile *)DMA3_X_MODIFY) /* DMA Channel 3 X Modify Register */
#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
#define pDMA3_Y_COUNT                  ((uint16_t volatile *)DMA3_Y_COUNT) /* DMA Channel 3 Y Count Register */
#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
#define pDMA3_Y_MODIFY                 ((uint16_t volatile *)DMA3_Y_MODIFY) /* DMA Channel 3 Y Modify Register */
#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
#define pDMA3_CURR_DESC_PTR            ((void * volatile *)DMA3_CURR_DESC_PTR) /* DMA Channel 3 Current Descriptor Pointer Register */
#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
#define pDMA3_CURR_ADDR                ((void * volatile *)DMA3_CURR_ADDR) /* DMA Channel 3 Current Address Register */
#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
#define pDMA3_IRQ_STATUS               ((uint16_t volatile *)DMA3_IRQ_STATUS) /* DMA Channel 3 Interrupt/Status Register */
#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
#define pDMA3_PERIPHERAL_MAP           ((uint16_t volatile *)DMA3_PERIPHERAL_MAP) /* DMA Channel 3 Peripheral Map Register */
#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
#define pDMA3_CURR_X_COUNT             ((uint16_t volatile *)DMA3_CURR_X_COUNT) /* DMA Channel 3 Current X Count Register */
#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
#define pDMA3_CURR_Y_COUNT             ((uint16_t volatile *)DMA3_CURR_Y_COUNT) /* DMA Channel 3 Current Y Count Register */
#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
#define pDMA4_NEXT_DESC_PTR            ((void * volatile *)DMA4_NEXT_DESC_PTR) /* DMA Channel 4 Next Descriptor Pointer Register */
#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
#define pDMA4_START_ADDR               ((void * volatile *)DMA4_START_ADDR) /* DMA Channel 4 Start Address Register */
#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
#define pDMA4_CONFIG                   ((uint16_t volatile *)DMA4_CONFIG) /* DMA Channel 4 Configuration Register */
#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
#define pDMA4_X_COUNT                  ((uint16_t volatile *)DMA4_X_COUNT) /* DMA Channel 4 X Count Register */
#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
#define pDMA4_X_MODIFY                 ((uint16_t volatile *)DMA4_X_MODIFY) /* DMA Channel 4 X Modify Register */
#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
#define pDMA4_Y_COUNT                  ((uint16_t volatile *)DMA4_Y_COUNT) /* DMA Channel 4 Y Count Register */
#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
#define pDMA4_Y_MODIFY                 ((uint16_t volatile *)DMA4_Y_MODIFY) /* DMA Channel 4 Y Modify Register */
#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
#define pDMA4_CURR_DESC_PTR            ((void * volatile *)DMA4_CURR_DESC_PTR) /* DMA Channel 4 Current Descriptor Pointer Register */
#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
#define pDMA4_CURR_ADDR                ((void * volatile *)DMA4_CURR_ADDR) /* DMA Channel 4 Current Address Register */
#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
#define pDMA4_IRQ_STATUS               ((uint16_t volatile *)DMA4_IRQ_STATUS) /* DMA Channel 4 Interrupt/Status Register */
#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
#define pDMA4_PERIPHERAL_MAP           ((uint16_t volatile *)DMA4_PERIPHERAL_MAP) /* DMA Channel 4 Peripheral Map Register */
#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
#define pDMA4_CURR_X_COUNT             ((uint16_t volatile *)DMA4_CURR_X_COUNT) /* DMA Channel 4 Current X Count Register */
#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
#define pDMA4_CURR_Y_COUNT             ((uint16_t volatile *)DMA4_CURR_Y_COUNT) /* DMA Channel 4 Current Y Count Register */
#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
#define pDMA5_NEXT_DESC_PTR            ((void * volatile *)DMA5_NEXT_DESC_PTR) /* DMA Channel 5 Next Descriptor Pointer Register */
#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
#define pDMA5_START_ADDR               ((void * volatile *)DMA5_START_ADDR) /* DMA Channel 5 Start Address Register */
#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
#define pDMA5_CONFIG                   ((uint16_t volatile *)DMA5_CONFIG) /* DMA Channel 5 Configuration Register */
#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
#define pDMA5_X_COUNT                  ((uint16_t volatile *)DMA5_X_COUNT) /* DMA Channel 5 X Count Register */
#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
#define pDMA5_X_MODIFY                 ((uint16_t volatile *)DMA5_X_MODIFY) /* DMA Channel 5 X Modify Register */
#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
#define pDMA5_Y_COUNT                  ((uint16_t volatile *)DMA5_Y_COUNT) /* DMA Channel 5 Y Count Register */
#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
#define pDMA5_Y_MODIFY                 ((uint16_t volatile *)DMA5_Y_MODIFY) /* DMA Channel 5 Y Modify Register */
#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
#define pDMA5_CURR_DESC_PTR            ((void * volatile *)DMA5_CURR_DESC_PTR) /* DMA Channel 5 Current Descriptor Pointer Register */
#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
#define pDMA5_CURR_ADDR                ((void * volatile *)DMA5_CURR_ADDR) /* DMA Channel 5 Current Address Register */
#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
#define pDMA5_IRQ_STATUS               ((uint16_t volatile *)DMA5_IRQ_STATUS) /* DMA Channel 5 Interrupt/Status Register */
#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
#define pDMA5_PERIPHERAL_MAP           ((uint16_t volatile *)DMA5_PERIPHERAL_MAP) /* DMA Channel 5 Peripheral Map Register */
#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
#define pDMA5_CURR_X_COUNT             ((uint16_t volatile *)DMA5_CURR_X_COUNT) /* DMA Channel 5 Current X Count Register */
#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
#define pDMA5_CURR_Y_COUNT             ((uint16_t volatile *)DMA5_CURR_Y_COUNT) /* DMA Channel 5 Current Y Count Register */
#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
#define pDMA6_NEXT_DESC_PTR            ((void * volatile *)DMA6_NEXT_DESC_PTR) /* DMA Channel 6 Next Descriptor Pointer Register */
#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_readPTR(DMA6_NEXT_DESC_PTR)
#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_writePTR(DMA6_NEXT_DESC_PTR, val)
#define pDMA6_START_ADDR               ((void * volatile *)DMA6_START_ADDR) /* DMA Channel 6 Start Address Register */
#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
#define pDMA6_CONFIG                   ((uint16_t volatile *)DMA6_CONFIG) /* DMA Channel 6 Configuration Register */
#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
#define pDMA6_X_COUNT                  ((uint16_t volatile *)DMA6_X_COUNT) /* DMA Channel 6 X Count Register */
#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
#define pDMA6_X_MODIFY                 ((uint16_t volatile *)DMA6_X_MODIFY) /* DMA Channel 6 X Modify Register */
#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
#define pDMA6_Y_COUNT                  ((uint16_t volatile *)DMA6_Y_COUNT) /* DMA Channel 6 Y Count Register */
#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
#define pDMA6_Y_MODIFY                 ((uint16_t volatile *)DMA6_Y_MODIFY) /* DMA Channel 6 Y Modify Register */
#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
#define pDMA6_CURR_DESC_PTR            ((void * volatile *)DMA6_CURR_DESC_PTR) /* DMA Channel 6 Current Descriptor Pointer Register */
#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
#define pDMA6_CURR_ADDR                ((void * volatile *)DMA6_CURR_ADDR) /* DMA Channel 6 Current Address Register */
#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
#define pDMA6_IRQ_STATUS               ((uint16_t volatile *)DMA6_IRQ_STATUS) /* DMA Channel 6 Interrupt/Status Register */
#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
#define pDMA6_PERIPHERAL_MAP           ((uint16_t volatile *)DMA6_PERIPHERAL_MAP) /* DMA Channel 6 Peripheral Map Register */
#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
#define pDMA6_CURR_X_COUNT             ((uint16_t volatile *)DMA6_CURR_X_COUNT) /* DMA Channel 6 Current X Count Register */
#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
#define pDMA6_CURR_Y_COUNT             ((uint16_t volatile *)DMA6_CURR_Y_COUNT) /* DMA Channel 6 Current Y Count Register */
#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
#define pDMA7_NEXT_DESC_PTR            ((void * volatile *)DMA7_NEXT_DESC_PTR) /* DMA Channel 7 Next Descriptor Pointer Register */
#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
#define pDMA7_START_ADDR               ((void * volatile *)DMA7_START_ADDR) /* DMA Channel 7 Start Address Register */
#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
#define pDMA7_CONFIG                   ((uint16_t volatile *)DMA7_CONFIG) /* DMA Channel 7 Configuration Register */
#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
#define pDMA7_X_COUNT                  ((uint16_t volatile *)DMA7_X_COUNT) /* DMA Channel 7 X Count Register */
#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
#define pDMA7_X_MODIFY                 ((uint16_t volatile *)DMA7_X_MODIFY) /* DMA Channel 7 X Modify Register */
#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
#define pDMA7_Y_COUNT                  ((uint16_t volatile *)DMA7_Y_COUNT) /* DMA Channel 7 Y Count Register */
#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
#define pDMA7_Y_MODIFY                 ((uint16_t volatile *)DMA7_Y_MODIFY) /* DMA Channel 7 Y Modify Register */
#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
#define pDMA7_CURR_DESC_PTR            ((void * volatile *)DMA7_CURR_DESC_PTR) /* DMA Channel 7 Current Descriptor Pointer Register */
#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
#define pDMA7_CURR_ADDR                ((void * volatile *)DMA7_CURR_ADDR) /* DMA Channel 7 Current Address Register */
#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
#define pDMA7_IRQ_STATUS               ((uint16_t volatile *)DMA7_IRQ_STATUS) /* DMA Channel 7 Interrupt/Status Register */
#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
#define pDMA7_PERIPHERAL_MAP           ((uint16_t volatile *)DMA7_PERIPHERAL_MAP) /* DMA Channel 7 Peripheral Map Register */
#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
#define pDMA7_CURR_X_COUNT             ((uint16_t volatile *)DMA7_CURR_X_COUNT) /* DMA Channel 7 Current X Count Register */
#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
#define pDMA7_CURR_Y_COUNT             ((uint16_t volatile *)DMA7_CURR_Y_COUNT) /* DMA Channel 7 Current Y Count Register */
#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
#define pDMA8_NEXT_DESC_PTR            ((void * volatile *)DMA8_NEXT_DESC_PTR) /* DMA Channel 8 Next Descriptor Pointer Register */
#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
#define pDMA8_START_ADDR               ((void * volatile *)DMA8_START_ADDR) /* DMA Channel 8 Start Address Register */
#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
#define pDMA8_CONFIG                   ((uint16_t volatile *)DMA8_CONFIG) /* DMA Channel 8 Configuration Register */
#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
#define pDMA8_X_COUNT                  ((uint16_t volatile *)DMA8_X_COUNT) /* DMA Channel 8 X Count Register */
#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
#define pDMA8_X_MODIFY                 ((uint16_t volatile *)DMA8_X_MODIFY) /* DMA Channel 8 X Modify Register */
#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
#define pDMA8_Y_COUNT                  ((uint16_t volatile *)DMA8_Y_COUNT) /* DMA Channel 8 Y Count Register */
#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
#define pDMA8_Y_MODIFY                 ((uint16_t volatile *)DMA8_Y_MODIFY) /* DMA Channel 8 Y Modify Register */
#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
#define pDMA8_CURR_DESC_PTR            ((void * volatile *)DMA8_CURR_DESC_PTR) /* DMA Channel 8 Current Descriptor Pointer Register */
#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
#define pDMA8_CURR_ADDR                ((void * volatile *)DMA8_CURR_ADDR) /* DMA Channel 8 Current Address Register */
#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
#define pDMA8_IRQ_STATUS               ((uint16_t volatile *)DMA8_IRQ_STATUS) /* DMA Channel 8 Interrupt/Status Register */
#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
#define pDMA8_PERIPHERAL_MAP           ((uint16_t volatile *)DMA8_PERIPHERAL_MAP) /* DMA Channel 8 Peripheral Map Register */
#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
#define pDMA8_CURR_X_COUNT             ((uint16_t volatile *)DMA8_CURR_X_COUNT) /* DMA Channel 8 Current X Count Register */
#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
#define pDMA8_CURR_Y_COUNT             ((uint16_t volatile *)DMA8_CURR_Y_COUNT) /* DMA Channel 8 Current Y Count Register */
#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
#define pDMA9_NEXT_DESC_PTR            ((void * volatile *)DMA9_NEXT_DESC_PTR) /* DMA Channel 9 Next Descriptor Pointer Register */
#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
#define pDMA9_START_ADDR               ((void * volatile *)DMA9_START_ADDR) /* DMA Channel 9 Start Address Register */
#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
#define pDMA9_CONFIG                   ((uint16_t volatile *)DMA9_CONFIG) /* DMA Channel 9 Configuration Register */
#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
#define pDMA9_X_COUNT                  ((uint16_t volatile *)DMA9_X_COUNT) /* DMA Channel 9 X Count Register */
#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
#define pDMA9_X_MODIFY                 ((uint16_t volatile *)DMA9_X_MODIFY) /* DMA Channel 9 X Modify Register */
#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
#define pDMA9_Y_COUNT                  ((uint16_t volatile *)DMA9_Y_COUNT) /* DMA Channel 9 Y Count Register */
#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
#define pDMA9_Y_MODIFY                 ((uint16_t volatile *)DMA9_Y_MODIFY) /* DMA Channel 9 Y Modify Register */
#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
#define pDMA9_CURR_DESC_PTR            ((void * volatile *)DMA9_CURR_DESC_PTR) /* DMA Channel 9 Current Descriptor Pointer Register */
#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
#define pDMA9_CURR_ADDR                ((void * volatile *)DMA9_CURR_ADDR) /* DMA Channel 9 Current Address Register */
#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
#define pDMA9_IRQ_STATUS               ((uint16_t volatile *)DMA9_IRQ_STATUS) /* DMA Channel 9 Interrupt/Status Register */
#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
#define pDMA9_PERIPHERAL_MAP           ((uint16_t volatile *)DMA9_PERIPHERAL_MAP) /* DMA Channel 9 Peripheral Map Register */
#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
#define pDMA9_CURR_X_COUNT             ((uint16_t volatile *)DMA9_CURR_X_COUNT) /* DMA Channel 9 Current X Count Register */
#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
#define pDMA9_CURR_Y_COUNT             ((uint16_t volatile *)DMA9_CURR_Y_COUNT) /* DMA Channel 9 Current Y Count Register */
#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
#define pDMA10_NEXT_DESC_PTR           ((void * volatile *)DMA10_NEXT_DESC_PTR) /* DMA Channel 10 Next Descriptor Pointer Register */
#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
#define pDMA10_START_ADDR              ((void * volatile *)DMA10_START_ADDR) /* DMA Channel 10 Start Address Register */
#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
#define pDMA10_CONFIG                  ((uint16_t volatile *)DMA10_CONFIG) /* DMA Channel 10 Configuration Register */
#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
#define pDMA10_X_COUNT                 ((uint16_t volatile *)DMA10_X_COUNT) /* DMA Channel 10 X Count Register */
#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
#define pDMA10_X_MODIFY                ((uint16_t volatile *)DMA10_X_MODIFY) /* DMA Channel 10 X Modify Register */
#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
#define pDMA10_Y_COUNT                 ((uint16_t volatile *)DMA10_Y_COUNT) /* DMA Channel 10 Y Count Register */
#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
#define pDMA10_Y_MODIFY                ((uint16_t volatile *)DMA10_Y_MODIFY) /* DMA Channel 10 Y Modify Register */
#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
#define pDMA10_CURR_DESC_PTR           ((void * volatile *)DMA10_CURR_DESC_PTR) /* DMA Channel 10 Current Descriptor Pointer Register */
#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
#define pDMA10_CURR_ADDR               ((void * volatile *)DMA10_CURR_ADDR) /* DMA Channel 10 Current Address Register */
#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
#define pDMA10_IRQ_STATUS              ((uint16_t volatile *)DMA10_IRQ_STATUS) /* DMA Channel 10 Interrupt/Status Register */
#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
#define pDMA10_PERIPHERAL_MAP          ((uint16_t volatile *)DMA10_PERIPHERAL_MAP) /* DMA Channel 10 Peripheral Map Register */
#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
#define pDMA10_CURR_X_COUNT            ((uint16_t volatile *)DMA10_CURR_X_COUNT) /* DMA Channel 10 Current X Count Register */
#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
#define pDMA10_CURR_Y_COUNT            ((uint16_t volatile *)DMA10_CURR_Y_COUNT) /* DMA Channel 10 Current Y Count Register */
#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
#define pDMA11_NEXT_DESC_PTR           ((void * volatile *)DMA11_NEXT_DESC_PTR) /* DMA Channel 11 Next Descriptor Pointer Register */
#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
#define pDMA11_START_ADDR              ((void * volatile *)DMA11_START_ADDR) /* DMA Channel 11 Start Address Register */
#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
#define pDMA11_CONFIG                  ((uint16_t volatile *)DMA11_CONFIG) /* DMA Channel 11 Configuration Register */
#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
#define pDMA11_X_COUNT                 ((uint16_t volatile *)DMA11_X_COUNT) /* DMA Channel 11 X Count Register */
#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
#define pDMA11_X_MODIFY                ((uint16_t volatile *)DMA11_X_MODIFY) /* DMA Channel 11 X Modify Register */
#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
#define pDMA11_Y_COUNT                 ((uint16_t volatile *)DMA11_Y_COUNT) /* DMA Channel 11 Y Count Register */
#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
#define pDMA11_Y_MODIFY                ((uint16_t volatile *)DMA11_Y_MODIFY) /* DMA Channel 11 Y Modify Register */
#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
#define pDMA11_CURR_DESC_PTR           ((void * volatile *)DMA11_CURR_DESC_PTR) /* DMA Channel 11 Current Descriptor Pointer Register */
#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
#define pDMA11_CURR_ADDR               ((void * volatile *)DMA11_CURR_ADDR) /* DMA Channel 11 Current Address Register */
#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
#define pDMA11_IRQ_STATUS              ((uint16_t volatile *)DMA11_IRQ_STATUS) /* DMA Channel 11 Interrupt/Status Register */
#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
#define pDMA11_PERIPHERAL_MAP          ((uint16_t volatile *)DMA11_PERIPHERAL_MAP) /* DMA Channel 11 Peripheral Map Register */
#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
#define pDMA11_CURR_X_COUNT            ((uint16_t volatile *)DMA11_CURR_X_COUNT) /* DMA Channel 11 Current X Count Register */
#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
#define pDMA11_CURR_Y_COUNT            ((uint16_t volatile *)DMA11_CURR_Y_COUNT) /* DMA Channel 11 Current Y Count Register */
#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
#define pDMA12_NEXT_DESC_PTR           ((void * volatile *)DMA12_NEXT_DESC_PTR) /* DMA Channel 12 Next Descriptor Pointer Register */
#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_readPTR(DMA12_NEXT_DESC_PTR)
#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_writePTR(DMA12_NEXT_DESC_PTR, val)
#define pDMA12_START_ADDR              ((void * volatile *)DMA12_START_ADDR) /* DMA Channel 12 Start Address Register */
#define bfin_read_DMA12_START_ADDR()   bfin_readPTR(DMA12_START_ADDR)
#define bfin_write_DMA12_START_ADDR(val) bfin_writePTR(DMA12_START_ADDR, val)
#define pDMA12_CONFIG                  ((uint16_t volatile *)DMA12_CONFIG) /* DMA Channel 12 Configuration Register */
#define bfin_read_DMA12_CONFIG()       bfin_read16(DMA12_CONFIG)
#define bfin_write_DMA12_CONFIG(val)   bfin_write16(DMA12_CONFIG, val)
#define pDMA12_X_COUNT                 ((uint16_t volatile *)DMA12_X_COUNT) /* DMA Channel 12 X Count Register */
#define bfin_read_DMA12_X_COUNT()      bfin_read16(DMA12_X_COUNT)
#define bfin_write_DMA12_X_COUNT(val)  bfin_write16(DMA12_X_COUNT, val)
#define pDMA12_X_MODIFY                ((uint16_t volatile *)DMA12_X_MODIFY) /* DMA Channel 12 X Modify Register */
#define bfin_read_DMA12_X_MODIFY()     bfin_read16(DMA12_X_MODIFY)
#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY, val)
#define pDMA12_Y_COUNT                 ((uint16_t volatile *)DMA12_Y_COUNT) /* DMA Channel 12 Y Count Register */
#define bfin_read_DMA12_Y_COUNT()      bfin_read16(DMA12_Y_COUNT)
#define bfin_write_DMA12_Y_COUNT(val)  bfin_write16(DMA12_Y_COUNT, val)
#define pDMA12_Y_MODIFY                ((uint16_t volatile *)DMA12_Y_MODIFY) /* DMA Channel 12 Y Modify Register */
#define bfin_read_DMA12_Y_MODIFY()     bfin_read16(DMA12_Y_MODIFY)
#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY, val)
#define pDMA12_CURR_DESC_PTR           ((void * volatile *)DMA12_CURR_DESC_PTR) /* DMA Channel 12 Current Descriptor Pointer Register */
#define bfin_read_DMA12_CURR_DESC_PTR() bfin_readPTR(DMA12_CURR_DESC_PTR)
#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_writePTR(DMA12_CURR_DESC_PTR, val)
#define pDMA12_CURR_ADDR               ((void * volatile *)DMA12_CURR_ADDR) /* DMA Channel 12 Current Address Register */
#define bfin_read_DMA12_CURR_ADDR()    bfin_readPTR(DMA12_CURR_ADDR)
#define bfin_write_DMA12_CURR_ADDR(val) bfin_writePTR(DMA12_CURR_ADDR, val)
#define pDMA12_IRQ_STATUS              ((uint16_t volatile *)DMA12_IRQ_STATUS) /* DMA Channel 12 Interrupt/Status Register */
#define bfin_read_DMA12_IRQ_STATUS()   bfin_read16(DMA12_IRQ_STATUS)
#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
#define pDMA12_PERIPHERAL_MAP          ((uint16_t volatile *)DMA12_PERIPHERAL_MAP) /* DMA Channel 12 Peripheral Map Register */
#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
#define pDMA12_CURR_X_COUNT            ((uint16_t volatile *)DMA12_CURR_X_COUNT) /* DMA Channel 12 Current X Count Register */
#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
#define pDMA12_CURR_Y_COUNT            ((uint16_t volatile *)DMA12_CURR_Y_COUNT) /* DMA Channel 12 Current Y Count Register */
#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
#define pDMA13_NEXT_DESC_PTR           ((void * volatile *)DMA13_NEXT_DESC_PTR) /* DMA Channel 13 Next Descriptor Pointer Register */
#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_readPTR(DMA13_NEXT_DESC_PTR)
#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_writePTR(DMA13_NEXT_DESC_PTR, val)
#define pDMA13_START_ADDR              ((void * volatile *)DMA13_START_ADDR) /* DMA Channel 13 Start Address Register */
#define bfin_read_DMA13_START_ADDR()   bfin_readPTR(DMA13_START_ADDR)
#define bfin_write_DMA13_START_ADDR(val) bfin_writePTR(DMA13_START_ADDR, val)
#define pDMA13_CONFIG                  ((uint16_t volatile *)DMA13_CONFIG) /* DMA Channel 13 Configuration Register */
#define bfin_read_DMA13_CONFIG()       bfin_read16(DMA13_CONFIG)
#define bfin_write_DMA13_CONFIG(val)   bfin_write16(DMA13_CONFIG, val)
#define pDMA13_X_COUNT                 ((uint16_t volatile *)DMA13_X_COUNT) /* DMA Channel 13 X Count Register */
#define bfin_read_DMA13_X_COUNT()      bfin_read16(DMA13_X_COUNT)
#define bfin_write_DMA13_X_COUNT(val)  bfin_write16(DMA13_X_COUNT, val)
#define pDMA13_X_MODIFY                ((uint16_t volatile *)DMA13_X_MODIFY) /* DMA Channel 13 X Modify Register */
#define bfin_read_DMA13_X_MODIFY()     bfin_read16(DMA13_X_MODIFY)
#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY, val)
#define pDMA13_Y_COUNT                 ((uint16_t volatile *)DMA13_Y_COUNT) /* DMA Channel 13 Y Count Register */
#define bfin_read_DMA13_Y_COUNT()      bfin_read16(DMA13_Y_COUNT)
#define bfin_write_DMA13_Y_COUNT(val)  bfin_write16(DMA13_Y_COUNT, val)
#define pDMA13_Y_MODIFY                ((uint16_t volatile *)DMA13_Y_MODIFY) /* DMA Channel 13 Y Modify Register */
#define bfin_read_DMA13_Y_MODIFY()     bfin_read16(DMA13_Y_MODIFY)
#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY, val)
#define pDMA13_CURR_DESC_PTR           ((void * volatile *)DMA13_CURR_DESC_PTR) /* DMA Channel 13 Current Descriptor Pointer Register */
#define bfin_read_DMA13_CURR_DESC_PTR() bfin_readPTR(DMA13_CURR_DESC_PTR)
#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_writePTR(DMA13_CURR_DESC_PTR, val)
#define pDMA13_CURR_ADDR               ((void * volatile *)DMA13_CURR_ADDR) /* DMA Channel 13 Current Address Register */
#define bfin_read_DMA13_CURR_ADDR()    bfin_readPTR(DMA13_CURR_ADDR)
#define bfin_write_DMA13_CURR_ADDR(val) bfin_writePTR(DMA13_CURR_ADDR, val)
#define pDMA13_IRQ_STATUS              ((uint16_t volatile *)DMA13_IRQ_STATUS) /* DMA Channel 13 Interrupt/Status Register */
#define bfin_read_DMA13_IRQ_STATUS()   bfin_read16(DMA13_IRQ_STATUS)
#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
#define pDMA13_PERIPHERAL_MAP          ((uint16_t volatile *)DMA13_PERIPHERAL_MAP) /* DMA Channel 13 Peripheral Map Register */
#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
#define pDMA13_CURR_X_COUNT            ((uint16_t volatile *)DMA13_CURR_X_COUNT) /* DMA Channel 13 Current X Count Register */
#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
#define pDMA13_CURR_Y_COUNT            ((uint16_t volatile *)DMA13_CURR_Y_COUNT) /* DMA Channel 13 Current Y Count Register */
#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
#define pDMA14_NEXT_DESC_PTR           ((void * volatile *)DMA14_NEXT_DESC_PTR) /* DMA Channel 14 Next Descriptor Pointer Register */
#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_readPTR(DMA14_NEXT_DESC_PTR)
#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_writePTR(DMA14_NEXT_DESC_PTR, val)
#define pDMA14_START_ADDR              ((void * volatile *)DMA14_START_ADDR) /* DMA Channel 14 Start Address Register */
#define bfin_read_DMA14_START_ADDR()   bfin_readPTR(DMA14_START_ADDR)
#define bfin_write_DMA14_START_ADDR(val) bfin_writePTR(DMA14_START_ADDR, val)
#define pDMA14_CONFIG                  ((uint16_t volatile *)DMA14_CONFIG) /* DMA Channel 14 Configuration Register */
#define bfin_read_DMA14_CONFIG()       bfin_read16(DMA14_CONFIG)
#define bfin_write_DMA14_CONFIG(val)   bfin_write16(DMA14_CONFIG, val)
#define pDMA14_X_COUNT                 ((uint16_t volatile *)DMA14_X_COUNT) /* DMA Channel 14 X Count Register */
#define bfin_read_DMA14_X_COUNT()      bfin_read16(DMA14_X_COUNT)
#define bfin_write_DMA14_X_COUNT(val)  bfin_write16(DMA14_X_COUNT, val)
#define pDMA14_X_MODIFY                ((uint16_t volatile *)DMA14_X_MODIFY) /* DMA Channel 14 X Modify Register */
#define bfin_read_DMA14_X_MODIFY()     bfin_read16(DMA14_X_MODIFY)
#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY, val)
#define pDMA14_Y_COUNT                 ((uint16_t volatile *)DMA14_Y_COUNT) /* DMA Channel 14 Y Count Register */
#define bfin_read_DMA14_Y_COUNT()      bfin_read16(DMA14_Y_COUNT)
#define bfin_write_DMA14_Y_COUNT(val)  bfin_write16(DMA14_Y_COUNT, val)
#define pDMA14_Y_MODIFY                ((uint16_t volatile *)DMA14_Y_MODIFY) /* DMA Channel 14 Y Modify Register */
#define bfin_read_DMA14_Y_MODIFY()     bfin_read16(DMA14_Y_MODIFY)
#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY, val)
#define pDMA14_CURR_DESC_PTR           ((void * volatile *)DMA14_CURR_DESC_PTR) /* DMA Channel 14 Current Descriptor Pointer Register */
#define bfin_read_DMA14_CURR_DESC_PTR() bfin_readPTR(DMA14_CURR_DESC_PTR)
#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_writePTR(DMA14_CURR_DESC_PTR, val)
#define pDMA14_CURR_ADDR               ((void * volatile *)DMA14_CURR_ADDR) /* DMA Channel 14 Current Address Register */
#define bfin_read_DMA14_CURR_ADDR()    bfin_readPTR(DMA14_CURR_ADDR)
#define bfin_write_DMA14_CURR_ADDR(val) bfin_writePTR(DMA14_CURR_ADDR, val)
#define pDMA14_IRQ_STATUS              ((uint16_t volatile *)DMA14_IRQ_STATUS) /* DMA Channel 14 Interrupt/Status Register */
#define bfin_read_DMA14_IRQ_STATUS()   bfin_read16(DMA14_IRQ_STATUS)
#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
#define pDMA14_PERIPHERAL_MAP          ((uint16_t volatile *)DMA14_PERIPHERAL_MAP) /* DMA Channel 14 Peripheral Map Register */
#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
#define pDMA14_CURR_X_COUNT            ((uint16_t volatile *)DMA14_CURR_X_COUNT) /* DMA Channel 14 Current X Count Register */
#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
#define pDMA14_CURR_Y_COUNT            ((uint16_t volatile *)DMA14_CURR_Y_COUNT) /* DMA Channel 14 Current Y Count Register */
#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
#define pDMA15_NEXT_DESC_PTR           ((void * volatile *)DMA15_NEXT_DESC_PTR) /* DMA Channel 15 Next Descriptor Pointer Register */
#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_readPTR(DMA15_NEXT_DESC_PTR)
#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_writePTR(DMA15_NEXT_DESC_PTR, val)
#define pDMA15_START_ADDR              ((void * volatile *)DMA15_START_ADDR) /* DMA Channel 15 Start Address Register */
#define bfin_read_DMA15_START_ADDR()   bfin_readPTR(DMA15_START_ADDR)
#define bfin_write_DMA15_START_ADDR(val) bfin_writePTR(DMA15_START_ADDR, val)
#define pDMA15_CONFIG                  ((uint16_t volatile *)DMA15_CONFIG) /* DMA Channel 15 Configuration Register */
#define bfin_read_DMA15_CONFIG()       bfin_read16(DMA15_CONFIG)
#define bfin_write_DMA15_CONFIG(val)   bfin_write16(DMA15_CONFIG, val)
#define pDMA15_X_COUNT                 ((uint16_t volatile *)DMA15_X_COUNT) /* DMA Channel 15 X Count Register */
#define bfin_read_DMA15_X_COUNT()      bfin_read16(DMA15_X_COUNT)
#define bfin_write_DMA15_X_COUNT(val)  bfin_write16(DMA15_X_COUNT, val)
#define pDMA15_X_MODIFY                ((uint16_t volatile *)DMA15_X_MODIFY) /* DMA Channel 15 X Modify Register */
#define bfin_read_DMA15_X_MODIFY()     bfin_read16(DMA15_X_MODIFY)
#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY, val)
#define pDMA15_Y_COUNT                 ((uint16_t volatile *)DMA15_Y_COUNT) /* DMA Channel 15 Y Count Register */
#define bfin_read_DMA15_Y_COUNT()      bfin_read16(DMA15_Y_COUNT)
#define bfin_write_DMA15_Y_COUNT(val)  bfin_write16(DMA15_Y_COUNT, val)
#define pDMA15_Y_MODIFY                ((uint16_t volatile *)DMA15_Y_MODIFY) /* DMA Channel 15 Y Modify Register */
#define bfin_read_DMA15_Y_MODIFY()     bfin_read16(DMA15_Y_MODIFY)
#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY, val)
#define pDMA15_CURR_DESC_PTR           ((void * volatile *)DMA15_CURR_DESC_PTR) /* DMA Channel 15 Current Descriptor Pointer Register */
#define bfin_read_DMA15_CURR_DESC_PTR() bfin_readPTR(DMA15_CURR_DESC_PTR)
#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_writePTR(DMA15_CURR_DESC_PTR, val)
#define pDMA15_CURR_ADDR               ((void * volatile *)DMA15_CURR_ADDR) /* DMA Channel 15 Current Address Register */
#define bfin_read_DMA15_CURR_ADDR()    bfin_readPTR(DMA15_CURR_ADDR)
#define bfin_write_DMA15_CURR_ADDR(val) bfin_writePTR(DMA15_CURR_ADDR, val)
#define pDMA15_IRQ_STATUS              ((uint16_t volatile *)DMA15_IRQ_STATUS) /* DMA Channel 15 Interrupt/Status Register */
#define bfin_read_DMA15_IRQ_STATUS()   bfin_read16(DMA15_IRQ_STATUS)
#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
#define pDMA15_PERIPHERAL_MAP          ((uint16_t volatile *)DMA15_PERIPHERAL_MAP) /* DMA Channel 15 Peripheral Map Register */
#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
#define pDMA15_CURR_X_COUNT            ((uint16_t volatile *)DMA15_CURR_X_COUNT) /* DMA Channel 15 Current X Count Register */
#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
#define pDMA15_CURR_Y_COUNT            ((uint16_t volatile *)DMA15_CURR_Y_COUNT) /* DMA Channel 15 Current Y Count Register */
#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
#define pDMA16_NEXT_DESC_PTR           ((void * volatile *)DMA16_NEXT_DESC_PTR) /* DMA Channel 16 Next Descriptor Pointer Register */
#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_readPTR(DMA16_NEXT_DESC_PTR)
#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_writePTR(DMA16_NEXT_DESC_PTR, val)
#define pDMA16_START_ADDR              ((void * volatile *)DMA16_START_ADDR) /* DMA Channel 16 Start Address Register */
#define bfin_read_DMA16_START_ADDR()   bfin_readPTR(DMA16_START_ADDR)
#define bfin_write_DMA16_START_ADDR(val) bfin_writePTR(DMA16_START_ADDR, val)
#define pDMA16_CONFIG                  ((uint16_t volatile *)DMA16_CONFIG) /* DMA Channel 16 Configuration Register */
#define bfin_read_DMA16_CONFIG()       bfin_read16(DMA16_CONFIG)
#define bfin_write_DMA16_CONFIG(val)   bfin_write16(DMA16_CONFIG, val)
#define pDMA16_X_COUNT                 ((uint16_t volatile *)DMA16_X_COUNT) /* DMA Channel 16 X Count Register */
#define bfin_read_DMA16_X_COUNT()      bfin_read16(DMA16_X_COUNT)
#define bfin_write_DMA16_X_COUNT(val)  bfin_write16(DMA16_X_COUNT, val)
#define pDMA16_X_MODIFY                ((uint16_t volatile *)DMA16_X_MODIFY) /* DMA Channel 16 X Modify Register */
#define bfin_read_DMA16_X_MODIFY()     bfin_read16(DMA16_X_MODIFY)
#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY, val)
#define pDMA16_Y_COUNT                 ((uint16_t volatile *)DMA16_Y_COUNT) /* DMA Channel 16 Y Count Register */
#define bfin_read_DMA16_Y_COUNT()      bfin_read16(DMA16_Y_COUNT)
#define bfin_write_DMA16_Y_COUNT(val)  bfin_write16(DMA16_Y_COUNT, val)
#define pDMA16_Y_MODIFY                ((uint16_t volatile *)DMA16_Y_MODIFY) /* DMA Channel 16 Y Modify Register */
#define bfin_read_DMA16_Y_MODIFY()     bfin_read16(DMA16_Y_MODIFY)
#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY, val)
#define pDMA16_CURR_DESC_PTR           ((void * volatile *)DMA16_CURR_DESC_PTR) /* DMA Channel 16 Current Descriptor Pointer Register */
#define bfin_read_DMA16_CURR_DESC_PTR() bfin_readPTR(DMA16_CURR_DESC_PTR)
#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_writePTR(DMA16_CURR_DESC_PTR, val)
#define pDMA16_CURR_ADDR               ((void * volatile *)DMA16_CURR_ADDR) /* DMA Channel 16 Current Address Register */
#define bfin_read_DMA16_CURR_ADDR()    bfin_readPTR(DMA16_CURR_ADDR)
#define bfin_write_DMA16_CURR_ADDR(val) bfin_writePTR(DMA16_CURR_ADDR, val)
#define pDMA16_IRQ_STATUS              ((uint16_t volatile *)DMA16_IRQ_STATUS) /* DMA Channel 16 Interrupt/Status Register */
#define bfin_read_DMA16_IRQ_STATUS()   bfin_read16(DMA16_IRQ_STATUS)
#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
#define pDMA16_PERIPHERAL_MAP          ((uint16_t volatile *)DMA16_PERIPHERAL_MAP) /* DMA Channel 16 Peripheral Map Register */
#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
#define pDMA16_CURR_X_COUNT            ((uint16_t volatile *)DMA16_CURR_X_COUNT) /* DMA Channel 16 Current X Count Register */
#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
#define pDMA16_CURR_Y_COUNT            ((uint16_t volatile *)DMA16_CURR_Y_COUNT) /* DMA Channel 16 Current Y Count Register */
#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
#define pDMA17_NEXT_DESC_PTR           ((void * volatile *)DMA17_NEXT_DESC_PTR) /* DMA Channel 17 Next Descriptor Pointer Register */
#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_readPTR(DMA17_NEXT_DESC_PTR)
#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_writePTR(DMA17_NEXT_DESC_PTR, val)
#define pDMA17_START_ADDR              ((void * volatile *)DMA17_START_ADDR) /* DMA Channel 17 Start Address Register */
#define bfin_read_DMA17_START_ADDR()   bfin_readPTR(DMA17_START_ADDR)
#define bfin_write_DMA17_START_ADDR(val) bfin_writePTR(DMA17_START_ADDR, val)
#define pDMA17_CONFIG                  ((uint16_t volatile *)DMA17_CONFIG) /* DMA Channel 17 Configuration Register */
#define bfin_read_DMA17_CONFIG()       bfin_read16(DMA17_CONFIG)
#define bfin_write_DMA17_CONFIG(val)   bfin_write16(DMA17_CONFIG, val)
#define pDMA17_X_COUNT                 ((uint16_t volatile *)DMA17_X_COUNT) /* DMA Channel 17 X Count Register */
#define bfin_read_DMA17_X_COUNT()      bfin_read16(DMA17_X_COUNT)
#define bfin_write_DMA17_X_COUNT(val)  bfin_write16(DMA17_X_COUNT, val)
#define pDMA17_X_MODIFY                ((uint16_t volatile *)DMA17_X_MODIFY) /* DMA Channel 17 X Modify Register */
#define bfin_read_DMA17_X_MODIFY()     bfin_read16(DMA17_X_MODIFY)
#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY, val)
#define pDMA17_Y_COUNT                 ((uint16_t volatile *)DMA17_Y_COUNT) /* DMA Channel 17 Y Count Register */
#define bfin_read_DMA17_Y_COUNT()      bfin_read16(DMA17_Y_COUNT)
#define bfin_write_DMA17_Y_COUNT(val)  bfin_write16(DMA17_Y_COUNT, val)
#define pDMA17_Y_MODIFY                ((uint16_t volatile *)DMA17_Y_MODIFY) /* DMA Channel 17 Y Modify Register */
#define bfin_read_DMA17_Y_MODIFY()     bfin_read16(DMA17_Y_MODIFY)
#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY, val)
#define pDMA17_CURR_DESC_PTR           ((void * volatile *)DMA17_CURR_DESC_PTR) /* DMA Channel 17 Current Descriptor Pointer Register */
#define bfin_read_DMA17_CURR_DESC_PTR() bfin_readPTR(DMA17_CURR_DESC_PTR)
#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_writePTR(DMA17_CURR_DESC_PTR, val)
#define pDMA17_CURR_ADDR               ((void * volatile *)DMA17_CURR_ADDR) /* DMA Channel 17 Current Address Register */
#define bfin_read_DMA17_CURR_ADDR()    bfin_readPTR(DMA17_CURR_ADDR)
#define bfin_write_DMA17_CURR_ADDR(val) bfin_writePTR(DMA17_CURR_ADDR, val)
#define pDMA17_IRQ_STATUS              ((uint16_t volatile *)DMA17_IRQ_STATUS) /* DMA Channel 17 Interrupt/Status Register */
#define bfin_read_DMA17_IRQ_STATUS()   bfin_read16(DMA17_IRQ_STATUS)
#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
#define pDMA17_PERIPHERAL_MAP          ((uint16_t volatile *)DMA17_PERIPHERAL_MAP) /* DMA Channel 17 Peripheral Map Register */
#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
#define pDMA17_CURR_X_COUNT            ((uint16_t volatile *)DMA17_CURR_X_COUNT) /* DMA Channel 17 Current X Count Register */
#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
#define pDMA17_CURR_Y_COUNT            ((uint16_t volatile *)DMA17_CURR_Y_COUNT) /* DMA Channel 17 Current Y Count Register */
#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
#define pDMA18_NEXT_DESC_PTR           ((void * volatile *)DMA18_NEXT_DESC_PTR) /* DMA Channel 18 Next Descriptor Pointer Register */
#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_readPTR(DMA18_NEXT_DESC_PTR)
#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_writePTR(DMA18_NEXT_DESC_PTR, val)
#define pDMA18_START_ADDR              ((void * volatile *)DMA18_START_ADDR) /* DMA Channel 18 Start Address Register */
#define bfin_read_DMA18_START_ADDR()   bfin_readPTR(DMA18_START_ADDR)
#define bfin_write_DMA18_START_ADDR(val) bfin_writePTR(DMA18_START_ADDR, val)
#define pDMA18_CONFIG                  ((uint16_t volatile *)DMA18_CONFIG) /* DMA Channel 18 Configuration Register */
#define bfin_read_DMA18_CONFIG()       bfin_read16(DMA18_CONFIG)
#define bfin_write_DMA18_CONFIG(val)   bfin_write16(DMA18_CONFIG, val)
#define pDMA18_X_COUNT                 ((uint16_t volatile *)DMA18_X_COUNT) /* DMA Channel 18 X Count Register */
#define bfin_read_DMA18_X_COUNT()      bfin_read16(DMA18_X_COUNT)
#define bfin_write_DMA18_X_COUNT(val)  bfin_write16(DMA18_X_COUNT, val)
#define pDMA18_X_MODIFY                ((uint16_t volatile *)DMA18_X_MODIFY) /* DMA Channel 18 X Modify Register */
#define bfin_read_DMA18_X_MODIFY()     bfin_read16(DMA18_X_MODIFY)
#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY, val)
#define pDMA18_Y_COUNT                 ((uint16_t volatile *)DMA18_Y_COUNT) /* DMA Channel 18 Y Count Register */
#define bfin_read_DMA18_Y_COUNT()      bfin_read16(DMA18_Y_COUNT)
#define bfin_write_DMA18_Y_COUNT(val)  bfin_write16(DMA18_Y_COUNT, val)
#define pDMA18_Y_MODIFY                ((uint16_t volatile *)DMA18_Y_MODIFY) /* DMA Channel 18 Y Modify Register */
#define bfin_read_DMA18_Y_MODIFY()     bfin_read16(DMA18_Y_MODIFY)
#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY, val)
#define pDMA18_CURR_DESC_PTR           ((void * volatile *)DMA18_CURR_DESC_PTR) /* DMA Channel 18 Current Descriptor Pointer Register */
#define bfin_read_DMA18_CURR_DESC_PTR() bfin_readPTR(DMA18_CURR_DESC_PTR)
#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_writePTR(DMA18_CURR_DESC_PTR, val)
#define pDMA18_CURR_ADDR               ((void * volatile *)DMA18_CURR_ADDR) /* DMA Channel 18 Current Address Register */
#define bfin_read_DMA18_CURR_ADDR()    bfin_readPTR(DMA18_CURR_ADDR)
#define bfin_write_DMA18_CURR_ADDR(val) bfin_writePTR(DMA18_CURR_ADDR, val)
#define pDMA18_IRQ_STATUS              ((uint16_t volatile *)DMA18_IRQ_STATUS) /* DMA Channel 18 Interrupt/Status Register */
#define bfin_read_DMA18_IRQ_STATUS()   bfin_read16(DMA18_IRQ_STATUS)
#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
#define pDMA18_PERIPHERAL_MAP          ((uint16_t volatile *)DMA18_PERIPHERAL_MAP) /* DMA Channel 18 Peripheral Map Register */
#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
#define pDMA18_CURR_X_COUNT            ((uint16_t volatile *)DMA18_CURR_X_COUNT) /* DMA Channel 18 Current X Count Register */
#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
#define pDMA18_CURR_Y_COUNT            ((uint16_t volatile *)DMA18_CURR_Y_COUNT) /* DMA Channel 18 Current Y Count Register */
#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
#define pDMA19_NEXT_DESC_PTR           ((void * volatile *)DMA19_NEXT_DESC_PTR) /* DMA Channel 19 Next Descriptor Pointer Register */
#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_readPTR(DMA19_NEXT_DESC_PTR)
#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_writePTR(DMA19_NEXT_DESC_PTR, val)
#define pDMA19_START_ADDR              ((void * volatile *)DMA19_START_ADDR) /* DMA Channel 19 Start Address Register */
#define bfin_read_DMA19_START_ADDR()   bfin_readPTR(DMA19_START_ADDR)
#define bfin_write_DMA19_START_ADDR(val) bfin_writePTR(DMA19_START_ADDR, val)
#define pDMA19_CONFIG                  ((uint16_t volatile *)DMA19_CONFIG) /* DMA Channel 19 Configuration Register */
#define bfin_read_DMA19_CONFIG()       bfin_read16(DMA19_CONFIG)
#define bfin_write_DMA19_CONFIG(val)   bfin_write16(DMA19_CONFIG, val)
#define pDMA19_X_COUNT                 ((uint16_t volatile *)DMA19_X_COUNT) /* DMA Channel 19 X Count Register */
#define bfin_read_DMA19_X_COUNT()      bfin_read16(DMA19_X_COUNT)
#define bfin_write_DMA19_X_COUNT(val)  bfin_write16(DMA19_X_COUNT, val)
#define pDMA19_X_MODIFY                ((uint16_t volatile *)DMA19_X_MODIFY) /* DMA Channel 19 X Modify Register */
#define bfin_read_DMA19_X_MODIFY()     bfin_read16(DMA19_X_MODIFY)
#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY, val)
#define pDMA19_Y_COUNT                 ((uint16_t volatile *)DMA19_Y_COUNT) /* DMA Channel 19 Y Count Register */
#define bfin_read_DMA19_Y_COUNT()      bfin_read16(DMA19_Y_COUNT)
#define bfin_write_DMA19_Y_COUNT(val)  bfin_write16(DMA19_Y_COUNT, val)
#define pDMA19_Y_MODIFY                ((uint16_t volatile *)DMA19_Y_MODIFY) /* DMA Channel 19 Y Modify Register */
#define bfin_read_DMA19_Y_MODIFY()     bfin_read16(DMA19_Y_MODIFY)
#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY, val)
#define pDMA19_CURR_DESC_PTR           ((void * volatile *)DMA19_CURR_DESC_PTR) /* DMA Channel 19 Current Descriptor Pointer Register */
#define bfin_read_DMA19_CURR_DESC_PTR() bfin_readPTR(DMA19_CURR_DESC_PTR)
#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_writePTR(DMA19_CURR_DESC_PTR, val)
#define pDMA19_CURR_ADDR               ((void * volatile *)DMA19_CURR_ADDR) /* DMA Channel 19 Current Address Register */
#define bfin_read_DMA19_CURR_ADDR()    bfin_readPTR(DMA19_CURR_ADDR)
#define bfin_write_DMA19_CURR_ADDR(val) bfin_writePTR(DMA19_CURR_ADDR, val)
#define pDMA19_IRQ_STATUS              ((uint16_t volatile *)DMA19_IRQ_STATUS) /* DMA Channel 19 Interrupt/Status Register */
#define bfin_read_DMA19_IRQ_STATUS()   bfin_read16(DMA19_IRQ_STATUS)
#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
#define pDMA19_PERIPHERAL_MAP          ((uint16_t volatile *)DMA19_PERIPHERAL_MAP) /* DMA Channel 19 Peripheral Map Register */
#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
#define pDMA19_CURR_X_COUNT            ((uint16_t volatile *)DMA19_CURR_X_COUNT) /* DMA Channel 19 Current X Count Register */
#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
#define pDMA19_CURR_Y_COUNT            ((uint16_t volatile *)DMA19_CURR_Y_COUNT) /* DMA Channel 19 Current Y Count Register */
#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
#define pDMA20_NEXT_DESC_PTR           ((void * volatile *)DMA20_NEXT_DESC_PTR) /* DMA Channel 20 Next Descriptor Pointer Register */
#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_readPTR(DMA20_NEXT_DESC_PTR)
#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_writePTR(DMA20_NEXT_DESC_PTR, val)
#define pDMA20_START_ADDR              ((void * volatile *)DMA20_START_ADDR) /* DMA Channel 20 Start Address Register */
#define bfin_read_DMA20_START_ADDR()   bfin_readPTR(DMA20_START_ADDR)
#define bfin_write_DMA20_START_ADDR(val) bfin_writePTR(DMA20_START_ADDR, val)
#define pDMA20_CONFIG                  ((uint16_t volatile *)DMA20_CONFIG) /* DMA Channel 20 Configuration Register */
#define bfin_read_DMA20_CONFIG()       bfin_read16(DMA20_CONFIG)
#define bfin_write_DMA20_CONFIG(val)   bfin_write16(DMA20_CONFIG, val)
#define pDMA20_X_COUNT                 ((uint16_t volatile *)DMA20_X_COUNT) /* DMA Channel 20 X Count Register */
#define bfin_read_DMA20_X_COUNT()      bfin_read16(DMA20_X_COUNT)
#define bfin_write_DMA20_X_COUNT(val)  bfin_write16(DMA20_X_COUNT, val)
#define pDMA20_X_MODIFY                ((uint16_t volatile *)DMA20_X_MODIFY) /* DMA Channel 20 X Modify Register */
#define bfin_read_DMA20_X_MODIFY()     bfin_read16(DMA20_X_MODIFY)
#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY, val)
#define pDMA20_Y_COUNT                 ((uint16_t volatile *)DMA20_Y_COUNT) /* DMA Channel 20 Y Count Register */
#define bfin_read_DMA20_Y_COUNT()      bfin_read16(DMA20_Y_COUNT)
#define bfin_write_DMA20_Y_COUNT(val)  bfin_write16(DMA20_Y_COUNT, val)
#define pDMA20_Y_MODIFY                ((uint16_t volatile *)DMA20_Y_MODIFY) /* DMA Channel 20 Y Modify Register */
#define bfin_read_DMA20_Y_MODIFY()     bfin_read16(DMA20_Y_MODIFY)
#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY, val)
#define pDMA20_CURR_DESC_PTR           ((void * volatile *)DMA20_CURR_DESC_PTR) /* DMA Channel 20 Current Descriptor Pointer Register */
#define bfin_read_DMA20_CURR_DESC_PTR() bfin_readPTR(DMA20_CURR_DESC_PTR)
#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_writePTR(DMA20_CURR_DESC_PTR, val)
#define pDMA20_CURR_ADDR               ((void * volatile *)DMA20_CURR_ADDR) /* DMA Channel 20 Current Address Register */
#define bfin_read_DMA20_CURR_ADDR()    bfin_readPTR(DMA20_CURR_ADDR)
#define bfin_write_DMA20_CURR_ADDR(val) bfin_writePTR(DMA20_CURR_ADDR, val)
#define pDMA20_IRQ_STATUS              ((uint16_t volatile *)DMA20_IRQ_STATUS) /* DMA Channel 20 Interrupt/Status Register */
#define bfin_read_DMA20_IRQ_STATUS()   bfin_read16(DMA20_IRQ_STATUS)
#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
#define pDMA20_PERIPHERAL_MAP          ((uint16_t volatile *)DMA20_PERIPHERAL_MAP) /* DMA Channel 20 Peripheral Map Register */
#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
#define pDMA20_CURR_X_COUNT            ((uint16_t volatile *)DMA20_CURR_X_COUNT) /* DMA Channel 20 Current X Count Register */
#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
#define pDMA20_CURR_Y_COUNT            ((uint16_t volatile *)DMA20_CURR_Y_COUNT) /* DMA Channel 20 Current Y Count Register */
#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
#define pDMA21_NEXT_DESC_PTR           ((void * volatile *)DMA21_NEXT_DESC_PTR) /* DMA Channel 21 Next Descriptor Pointer Register */
#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_readPTR(DMA21_NEXT_DESC_PTR)
#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_writePTR(DMA21_NEXT_DESC_PTR, val)
#define pDMA21_START_ADDR              ((void * volatile *)DMA21_START_ADDR) /* DMA Channel 21 Start Address Register */
#define bfin_read_DMA21_START_ADDR()   bfin_readPTR(DMA21_START_ADDR)
#define bfin_write_DMA21_START_ADDR(val) bfin_writePTR(DMA21_START_ADDR, val)
#define pDMA21_CONFIG                  ((uint16_t volatile *)DMA21_CONFIG) /* DMA Channel 21 Configuration Register */
#define bfin_read_DMA21_CONFIG()       bfin_read16(DMA21_CONFIG)
#define bfin_write_DMA21_CONFIG(val)   bfin_write16(DMA21_CONFIG, val)
#define pDMA21_X_COUNT                 ((uint16_t volatile *)DMA21_X_COUNT) /* DMA Channel 21 X Count Register */
#define bfin_read_DMA21_X_COUNT()      bfin_read16(DMA21_X_COUNT)
#define bfin_write_DMA21_X_COUNT(val)  bfin_write16(DMA21_X_COUNT, val)
#define pDMA21_X_MODIFY                ((uint16_t volatile *)DMA21_X_MODIFY) /* DMA Channel 21 X Modify Register */
#define bfin_read_DMA21_X_MODIFY()     bfin_read16(DMA21_X_MODIFY)
#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY, val)
#define pDMA21_Y_COUNT                 ((uint16_t volatile *)DMA21_Y_COUNT) /* DMA Channel 21 Y Count Register */
#define bfin_read_DMA21_Y_COUNT()      bfin_read16(DMA21_Y_COUNT)
#define bfin_write_DMA21_Y_COUNT(val)  bfin_write16(DMA21_Y_COUNT, val)
#define pDMA21_Y_MODIFY                ((uint16_t volatile *)DMA21_Y_MODIFY) /* DMA Channel 21 Y Modify Register */
#define bfin_read_DMA21_Y_MODIFY()     bfin_read16(DMA21_Y_MODIFY)
#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY, val)
#define pDMA21_CURR_DESC_PTR           ((void * volatile *)DMA21_CURR_DESC_PTR) /* DMA Channel 21 Current Descriptor Pointer Register */
#define bfin_read_DMA21_CURR_DESC_PTR() bfin_readPTR(DMA21_CURR_DESC_PTR)
#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_writePTR(DMA21_CURR_DESC_PTR, val)
#define pDMA21_CURR_ADDR               ((void * volatile *)DMA21_CURR_ADDR) /* DMA Channel 21 Current Address Register */
#define bfin_read_DMA21_CURR_ADDR()    bfin_readPTR(DMA21_CURR_ADDR)
#define bfin_write_DMA21_CURR_ADDR(val) bfin_writePTR(DMA21_CURR_ADDR, val)
#define pDMA21_IRQ_STATUS              ((uint16_t volatile *)DMA21_IRQ_STATUS) /* DMA Channel 21 Interrupt/Status Register */
#define bfin_read_DMA21_IRQ_STATUS()   bfin_read16(DMA21_IRQ_STATUS)
#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
#define pDMA21_PERIPHERAL_MAP          ((uint16_t volatile *)DMA21_PERIPHERAL_MAP) /* DMA Channel 21 Peripheral Map Register */
#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
#define pDMA21_CURR_X_COUNT            ((uint16_t volatile *)DMA21_CURR_X_COUNT) /* DMA Channel 21 Current X Count Register */
#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
#define pDMA21_CURR_Y_COUNT            ((uint16_t volatile *)DMA21_CURR_Y_COUNT) /* DMA Channel 21 Current Y Count Register */
#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
#define pDMA22_NEXT_DESC_PTR           ((void * volatile *)DMA22_NEXT_DESC_PTR) /* DMA Channel 22 Next Descriptor Pointer Register */
#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_readPTR(DMA22_NEXT_DESC_PTR)
#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_writePTR(DMA22_NEXT_DESC_PTR, val)
#define pDMA22_START_ADDR              ((void * volatile *)DMA22_START_ADDR) /* DMA Channel 22 Start Address Register */
#define bfin_read_DMA22_START_ADDR()   bfin_readPTR(DMA22_START_ADDR)
#define bfin_write_DMA22_START_ADDR(val) bfin_writePTR(DMA22_START_ADDR, val)
#define pDMA22_CONFIG                  ((uint16_t volatile *)DMA22_CONFIG) /* DMA Channel 22 Configuration Register */
#define bfin_read_DMA22_CONFIG()       bfin_read16(DMA22_CONFIG)
#define bfin_write_DMA22_CONFIG(val)   bfin_write16(DMA22_CONFIG, val)
#define pDMA22_X_COUNT                 ((uint16_t volatile *)DMA22_X_COUNT) /* DMA Channel 22 X Count Register */
#define bfin_read_DMA22_X_COUNT()      bfin_read16(DMA22_X_COUNT)
#define bfin_write_DMA22_X_COUNT(val)  bfin_write16(DMA22_X_COUNT, val)
#define pDMA22_X_MODIFY                ((uint16_t volatile *)DMA22_X_MODIFY) /* DMA Channel 22 X Modify Register */
#define bfin_read_DMA22_X_MODIFY()     bfin_read16(DMA22_X_MODIFY)
#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY, val)
#define pDMA22_Y_COUNT                 ((uint16_t volatile *)DMA22_Y_COUNT) /* DMA Channel 22 Y Count Register */
#define bfin_read_DMA22_Y_COUNT()      bfin_read16(DMA22_Y_COUNT)
#define bfin_write_DMA22_Y_COUNT(val)  bfin_write16(DMA22_Y_COUNT, val)
#define pDMA22_Y_MODIFY                ((uint16_t volatile *)DMA22_Y_MODIFY) /* DMA Channel 22 Y Modify Register */
#define bfin_read_DMA22_Y_MODIFY()     bfin_read16(DMA22_Y_MODIFY)
#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY, val)
#define pDMA22_CURR_DESC_PTR           ((void * volatile *)DMA22_CURR_DESC_PTR) /* DMA Channel 22 Current Descriptor Pointer Register */
#define bfin_read_DMA22_CURR_DESC_PTR() bfin_readPTR(DMA22_CURR_DESC_PTR)
#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_writePTR(DMA22_CURR_DESC_PTR, val)
#define pDMA22_CURR_ADDR               ((void * volatile *)DMA22_CURR_ADDR) /* DMA Channel 22 Current Address Register */
#define bfin_read_DMA22_CURR_ADDR()    bfin_readPTR(DMA22_CURR_ADDR)
#define bfin_write_DMA22_CURR_ADDR(val) bfin_writePTR(DMA22_CURR_ADDR, val)
#define pDMA22_IRQ_STATUS              ((uint16_t volatile *)DMA22_IRQ_STATUS) /* DMA Channel 22 Interrupt/Status Register */
#define bfin_read_DMA22_IRQ_STATUS()   bfin_read16(DMA22_IRQ_STATUS)
#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
#define pDMA22_PERIPHERAL_MAP          ((uint16_t volatile *)DMA22_PERIPHERAL_MAP) /* DMA Channel 22 Peripheral Map Register */
#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
#define pDMA22_CURR_X_COUNT            ((uint16_t volatile *)DMA22_CURR_X_COUNT) /* DMA Channel 22 Current X Count Register */
#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
#define pDMA22_CURR_Y_COUNT            ((uint16_t volatile *)DMA22_CURR_Y_COUNT) /* DMA Channel 22 Current Y Count Register */
#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
#define pDMA23_NEXT_DESC_PTR           ((void * volatile *)DMA23_NEXT_DESC_PTR) /* DMA Channel 23 Next Descriptor Pointer Register */
#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_readPTR(DMA23_NEXT_DESC_PTR)
#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_writePTR(DMA23_NEXT_DESC_PTR, val)
#define pDMA23_START_ADDR              ((void * volatile *)DMA23_START_ADDR) /* DMA Channel 23 Start Address Register */
#define bfin_read_DMA23_START_ADDR()   bfin_readPTR(DMA23_START_ADDR)
#define bfin_write_DMA23_START_ADDR(val) bfin_writePTR(DMA23_START_ADDR, val)
#define pDMA23_CONFIG                  ((uint16_t volatile *)DMA23_CONFIG) /* DMA Channel 23 Configuration Register */
#define bfin_read_DMA23_CONFIG()       bfin_read16(DMA23_CONFIG)
#define bfin_write_DMA23_CONFIG(val)   bfin_write16(DMA23_CONFIG, val)
#define pDMA23_X_COUNT                 ((uint16_t volatile *)DMA23_X_COUNT) /* DMA Channel 23 X Count Register */
#define bfin_read_DMA23_X_COUNT()      bfin_read16(DMA23_X_COUNT)
#define bfin_write_DMA23_X_COUNT(val)  bfin_write16(DMA23_X_COUNT, val)
#define pDMA23_X_MODIFY                ((uint16_t volatile *)DMA23_X_MODIFY) /* DMA Channel 23 X Modify Register */
#define bfin_read_DMA23_X_MODIFY()     bfin_read16(DMA23_X_MODIFY)
#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY, val)
#define pDMA23_Y_COUNT                 ((uint16_t volatile *)DMA23_Y_COUNT) /* DMA Channel 23 Y Count Register */
#define bfin_read_DMA23_Y_COUNT()      bfin_read16(DMA23_Y_COUNT)
#define bfin_write_DMA23_Y_COUNT(val)  bfin_write16(DMA23_Y_COUNT, val)
#define pDMA23_Y_MODIFY                ((uint16_t volatile *)DMA23_Y_MODIFY) /* DMA Channel 23 Y Modify Register */
#define bfin_read_DMA23_Y_MODIFY()     bfin_read16(DMA23_Y_MODIFY)
#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY, val)
#define pDMA23_CURR_DESC_PTR           ((void * volatile *)DMA23_CURR_DESC_PTR) /* DMA Channel 23 Current Descriptor Pointer Register */
#define bfin_read_DMA23_CURR_DESC_PTR() bfin_readPTR(DMA23_CURR_DESC_PTR)
#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_writePTR(DMA23_CURR_DESC_PTR, val)
#define pDMA23_CURR_ADDR               ((void * volatile *)DMA23_CURR_ADDR) /* DMA Channel 23 Current Address Register */
#define bfin_read_DMA23_CURR_ADDR()    bfin_readPTR(DMA23_CURR_ADDR)
#define bfin_write_DMA23_CURR_ADDR(val) bfin_writePTR(DMA23_CURR_ADDR, val)
#define pDMA23_IRQ_STATUS              ((uint16_t volatile *)DMA23_IRQ_STATUS) /* DMA Channel 23 Interrupt/Status Register */
#define bfin_read_DMA23_IRQ_STATUS()   bfin_read16(DMA23_IRQ_STATUS)
#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
#define pDMA23_PERIPHERAL_MAP          ((uint16_t volatile *)DMA23_PERIPHERAL_MAP) /* DMA Channel 23 Peripheral Map Register */
#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
#define pDMA23_CURR_X_COUNT            ((uint16_t volatile *)DMA23_CURR_X_COUNT) /* DMA Channel 23 Current X Count Register */
#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
#define pDMA23_CURR_Y_COUNT            ((uint16_t volatile *)DMA23_CURR_Y_COUNT) /* DMA Channel 23 Current Y Count Register */
#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
#define pMDMA_D0_NEXT_DESC_PTR         ((void * volatile *)MDMA_D0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
#define pMDMA_D0_START_ADDR            ((void * volatile *)MDMA_D0_START_ADDR) /* Memory DMA Stream 0 Destination Start Address Register */
#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
#define pMDMA_D0_CONFIG                ((uint16_t volatile *)MDMA_D0_CONFIG) /* Memory DMA Stream 0 Destination Configuration Register */
#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
#define pMDMA_D0_X_COUNT               ((uint16_t volatile *)MDMA_D0_X_COUNT) /* Memory DMA Stream 0 Destination X Count Register */
#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
#define pMDMA_D0_X_MODIFY              ((uint16_t volatile *)MDMA_D0_X_MODIFY) /* Memory DMA Stream 0 Destination X Modify Register */
#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
#define pMDMA_D0_Y_COUNT               ((uint16_t volatile *)MDMA_D0_Y_COUNT) /* Memory DMA Stream 0 Destination Y Count Register */
#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
#define pMDMA_D0_Y_MODIFY              ((uint16_t volatile *)MDMA_D0_Y_MODIFY) /* Memory DMA Stream 0 Destination Y Modify Register */
#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
#define pMDMA_D0_CURR_DESC_PTR         ((void * volatile *)MDMA_D0_CURR_DESC_PTR) /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
#define pMDMA_D0_CURR_ADDR             ((void * volatile *)MDMA_D0_CURR_ADDR) /* Memory DMA Stream 0 Destination Current Address Register */
#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
#define pMDMA_D0_IRQ_STATUS            ((uint16_t volatile *)MDMA_D0_IRQ_STATUS) /* Memory DMA Stream 0 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
#define pMDMA_D0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Destination Peripheral Map Register */
#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
#define pMDMA_D0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_X_COUNT) /* Memory DMA Stream 0 Destination Current X Count Register */
#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
#define pMDMA_D0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D0_CURR_Y_COUNT) /* Memory DMA Stream 0 Destination Current Y Count Register */
#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
#define pMDMA_S0_NEXT_DESC_PTR         ((void * volatile *)MDMA_S0_NEXT_DESC_PTR) /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
#define pMDMA_S0_START_ADDR            ((void * volatile *)MDMA_S0_START_ADDR) /* Memory DMA Stream 0 Source Start Address Register */
#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
#define pMDMA_S0_CONFIG                ((uint16_t volatile *)MDMA_S0_CONFIG) /* Memory DMA Stream 0 Source Configuration Register */
#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
#define pMDMA_S0_X_COUNT               ((uint16_t volatile *)MDMA_S0_X_COUNT) /* Memory DMA Stream 0 Source X Count Register */
#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
#define pMDMA_S0_X_MODIFY              ((uint16_t volatile *)MDMA_S0_X_MODIFY) /* Memory DMA Stream 0 Source X Modify Register */
#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
#define pMDMA_S0_Y_COUNT               ((uint16_t volatile *)MDMA_S0_Y_COUNT) /* Memory DMA Stream 0 Source Y Count Register */
#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
#define pMDMA_S0_Y_MODIFY              ((uint16_t volatile *)MDMA_S0_Y_MODIFY) /* Memory DMA Stream 0 Source Y Modify Register */
#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
#define pMDMA_S0_CURR_DESC_PTR         ((void * volatile *)MDMA_S0_CURR_DESC_PTR) /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
#define pMDMA_S0_CURR_ADDR             ((void * volatile *)MDMA_S0_CURR_ADDR) /* Memory DMA Stream 0 Source Current Address Register */
#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
#define pMDMA_S0_IRQ_STATUS            ((uint16_t volatile *)MDMA_S0_IRQ_STATUS) /* Memory DMA Stream 0 Source Interrupt/Status Register */
#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
#define pMDMA_S0_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S0_PERIPHERAL_MAP) /* Memory DMA Stream 0 Source Peripheral Map Register */
#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
#define pMDMA_S0_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_X_COUNT) /* Memory DMA Stream 0 Source Current X Count Register */
#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
#define pMDMA_S0_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S0_CURR_Y_COUNT) /* Memory DMA Stream 0 Source Current Y Count Register */
#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
#define pMDMA_D1_NEXT_DESC_PTR         ((void * volatile *)MDMA_D1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
#define pMDMA_D1_START_ADDR            ((void * volatile *)MDMA_D1_START_ADDR) /* Memory DMA Stream 1 Destination Start Address Register */
#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
#define pMDMA_D1_CONFIG                ((uint16_t volatile *)MDMA_D1_CONFIG) /* Memory DMA Stream 1 Destination Configuration Register */
#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
#define pMDMA_D1_X_COUNT               ((uint16_t volatile *)MDMA_D1_X_COUNT) /* Memory DMA Stream 1 Destination X Count Register */
#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
#define pMDMA_D1_X_MODIFY              ((uint16_t volatile *)MDMA_D1_X_MODIFY) /* Memory DMA Stream 1 Destination X Modify Register */
#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
#define pMDMA_D1_Y_COUNT               ((uint16_t volatile *)MDMA_D1_Y_COUNT) /* Memory DMA Stream 1 Destination Y Count Register */
#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
#define pMDMA_D1_Y_MODIFY              ((uint16_t volatile *)MDMA_D1_Y_MODIFY) /* Memory DMA Stream 1 Destination Y Modify Register */
#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
#define pMDMA_D1_CURR_DESC_PTR         ((void * volatile *)MDMA_D1_CURR_DESC_PTR) /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
#define pMDMA_D1_CURR_ADDR             ((void * volatile *)MDMA_D1_CURR_ADDR) /* Memory DMA Stream 1 Destination Current Address Register */
#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
#define pMDMA_D1_IRQ_STATUS            ((uint16_t volatile *)MDMA_D1_IRQ_STATUS) /* Memory DMA Stream 1 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
#define pMDMA_D1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Destination Peripheral Map Register */
#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
#define pMDMA_D1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_X_COUNT) /* Memory DMA Stream 1 Destination Current X Count Register */
#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
#define pMDMA_D1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D1_CURR_Y_COUNT) /* Memory DMA Stream 1 Destination Current Y Count Register */
#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
#define pMDMA_S1_NEXT_DESC_PTR         ((void * volatile *)MDMA_S1_NEXT_DESC_PTR) /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
#define pMDMA_S1_START_ADDR            ((void * volatile *)MDMA_S1_START_ADDR) /* Memory DMA Stream 1 Source Start Address Register */
#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
#define pMDMA_S1_CONFIG                ((uint16_t volatile *)MDMA_S1_CONFIG) /* Memory DMA Stream 1 Source Configuration Register */
#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
#define pMDMA_S1_X_COUNT               ((uint16_t volatile *)MDMA_S1_X_COUNT) /* Memory DMA Stream 1 Source X Count Register */
#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
#define pMDMA_S1_X_MODIFY              ((uint16_t volatile *)MDMA_S1_X_MODIFY) /* Memory DMA Stream 1 Source X Modify Register */
#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
#define pMDMA_S1_Y_COUNT               ((uint16_t volatile *)MDMA_S1_Y_COUNT) /* Memory DMA Stream 1 Source Y Count Register */
#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
#define pMDMA_S1_Y_MODIFY              ((uint16_t volatile *)MDMA_S1_Y_MODIFY) /* Memory DMA Stream 1 Source Y Modify Register */
#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
#define pMDMA_S1_CURR_DESC_PTR         ((void * volatile *)MDMA_S1_CURR_DESC_PTR) /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
#define pMDMA_S1_CURR_ADDR             ((void * volatile *)MDMA_S1_CURR_ADDR) /* Memory DMA Stream 1 Source Current Address Register */
#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
#define pMDMA_S1_IRQ_STATUS            ((uint16_t volatile *)MDMA_S1_IRQ_STATUS) /* Memory DMA Stream 1 Source Interrupt/Status Register */
#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
#define pMDMA_S1_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S1_PERIPHERAL_MAP) /* Memory DMA Stream 1 Source Peripheral Map Register */
#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
#define pMDMA_S1_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_X_COUNT) /* Memory DMA Stream 1 Source Current X Count Register */
#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
#define pMDMA_S1_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S1_CURR_Y_COUNT) /* Memory DMA Stream 1 Source Current Y Count Register */
#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
#define pMDMA_D2_NEXT_DESC_PTR         ((void * volatile *)MDMA_D2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_readPTR(MDMA_D2_NEXT_DESC_PTR)
#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D2_NEXT_DESC_PTR, val)
#define pMDMA_D2_START_ADDR            ((void * volatile *)MDMA_D2_START_ADDR) /* Memory DMA Stream 2 Destination Start Address Register */
#define bfin_read_MDMA_D2_START_ADDR() bfin_readPTR(MDMA_D2_START_ADDR)
#define bfin_write_MDMA_D2_START_ADDR(val) bfin_writePTR(MDMA_D2_START_ADDR, val)
#define pMDMA_D2_CONFIG                ((uint16_t volatile *)MDMA_D2_CONFIG) /* Memory DMA Stream 2 Destination Configuration Register */
#define bfin_read_MDMA_D2_CONFIG()     bfin_read16(MDMA_D2_CONFIG)
#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
#define pMDMA_D2_X_COUNT               ((uint16_t volatile *)MDMA_D2_X_COUNT) /* Memory DMA Stream 2 Destination X Count Register */
#define bfin_read_MDMA_D2_X_COUNT()    bfin_read16(MDMA_D2_X_COUNT)
#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
#define pMDMA_D2_X_MODIFY              ((uint16_t volatile *)MDMA_D2_X_MODIFY) /* Memory DMA Stream 2 Destination X Modify Register */
#define bfin_read_MDMA_D2_X_MODIFY()   bfin_read16(MDMA_D2_X_MODIFY)
#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY, val)
#define pMDMA_D2_Y_COUNT               ((uint16_t volatile *)MDMA_D2_Y_COUNT) /* Memory DMA Stream 2 Destination Y Count Register */
#define bfin_read_MDMA_D2_Y_COUNT()    bfin_read16(MDMA_D2_Y_COUNT)
#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
#define pMDMA_D2_Y_MODIFY              ((uint16_t volatile *)MDMA_D2_Y_MODIFY) /* Memory DMA Stream 2 Destination Y Modify Register */
#define bfin_read_MDMA_D2_Y_MODIFY()   bfin_read16(MDMA_D2_Y_MODIFY)
#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY, val)
#define pMDMA_D2_CURR_DESC_PTR         ((void * volatile *)MDMA_D2_CURR_DESC_PTR) /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_readPTR(MDMA_D2_CURR_DESC_PTR)
#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D2_CURR_DESC_PTR, val)
#define pMDMA_D2_CURR_ADDR             ((void * volatile *)MDMA_D2_CURR_ADDR) /* Memory DMA Stream 2 Destination Current Address Register */
#define bfin_read_MDMA_D2_CURR_ADDR()  bfin_readPTR(MDMA_D2_CURR_ADDR)
#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_writePTR(MDMA_D2_CURR_ADDR, val)
#define pMDMA_D2_IRQ_STATUS            ((uint16_t volatile *)MDMA_D2_IRQ_STATUS) /* Memory DMA Stream 2 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
#define pMDMA_D2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Destination Peripheral Map Register */
#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
#define pMDMA_D2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_X_COUNT) /* Memory DMA Stream 2 Destination Current X Count Register */
#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
#define pMDMA_D2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D2_CURR_Y_COUNT) /* Memory DMA Stream 2 Destination Current Y Count Register */
#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
#define pMDMA_S2_NEXT_DESC_PTR         ((void * volatile *)MDMA_S2_NEXT_DESC_PTR) /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_readPTR(MDMA_S2_NEXT_DESC_PTR)
#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S2_NEXT_DESC_PTR, val)
#define pMDMA_S2_START_ADDR            ((void * volatile *)MDMA_S2_START_ADDR) /* Memory DMA Stream 2 Source Start Address Register */
#define bfin_read_MDMA_S2_START_ADDR() bfin_readPTR(MDMA_S2_START_ADDR)
#define bfin_write_MDMA_S2_START_ADDR(val) bfin_writePTR(MDMA_S2_START_ADDR, val)
#define pMDMA_S2_CONFIG                ((uint16_t volatile *)MDMA_S2_CONFIG) /* Memory DMA Stream 2 Source Configuration Register */
#define bfin_read_MDMA_S2_CONFIG()     bfin_read16(MDMA_S2_CONFIG)
#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
#define pMDMA_S2_X_COUNT               ((uint16_t volatile *)MDMA_S2_X_COUNT) /* Memory DMA Stream 2 Source X Count Register */
#define bfin_read_MDMA_S2_X_COUNT()    bfin_read16(MDMA_S2_X_COUNT)
#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
#define pMDMA_S2_X_MODIFY              ((uint16_t volatile *)MDMA_S2_X_MODIFY) /* Memory DMA Stream 2 Source X Modify Register */
#define bfin_read_MDMA_S2_X_MODIFY()   bfin_read16(MDMA_S2_X_MODIFY)
#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY, val)
#define pMDMA_S2_Y_COUNT               ((uint16_t volatile *)MDMA_S2_Y_COUNT) /* Memory DMA Stream 2 Source Y Count Register */
#define bfin_read_MDMA_S2_Y_COUNT()    bfin_read16(MDMA_S2_Y_COUNT)
#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
#define pMDMA_S2_Y_MODIFY              ((uint16_t volatile *)MDMA_S2_Y_MODIFY) /* Memory DMA Stream 2 Source Y Modify Register */
#define bfin_read_MDMA_S2_Y_MODIFY()   bfin_read16(MDMA_S2_Y_MODIFY)
#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY, val)
#define pMDMA_S2_CURR_DESC_PTR         ((void * volatile *)MDMA_S2_CURR_DESC_PTR) /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_readPTR(MDMA_S2_CURR_DESC_PTR)
#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S2_CURR_DESC_PTR, val)
#define pMDMA_S2_CURR_ADDR             ((void * volatile *)MDMA_S2_CURR_ADDR) /* Memory DMA Stream 2 Source Current Address Register */
#define bfin_read_MDMA_S2_CURR_ADDR()  bfin_readPTR(MDMA_S2_CURR_ADDR)
#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_writePTR(MDMA_S2_CURR_ADDR, val)
#define pMDMA_S2_IRQ_STATUS            ((uint16_t volatile *)MDMA_S2_IRQ_STATUS) /* Memory DMA Stream 2 Source Interrupt/Status Register */
#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
#define pMDMA_S2_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S2_PERIPHERAL_MAP) /* Memory DMA Stream 2 Source Peripheral Map Register */
#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
#define pMDMA_S2_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_X_COUNT) /* Memory DMA Stream 2 Source Current X Count Register */
#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
#define pMDMA_S2_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S2_CURR_Y_COUNT) /* Memory DMA Stream 2 Source Current Y Count Register */
#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
#define pMDMA_D3_NEXT_DESC_PTR         ((void * volatile *)MDMA_D3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_readPTR(MDMA_D3_NEXT_DESC_PTR)
#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D3_NEXT_DESC_PTR, val)
#define pMDMA_D3_START_ADDR            ((void * volatile *)MDMA_D3_START_ADDR) /* Memory DMA Stream 3 Destination Start Address Register */
#define bfin_read_MDMA_D3_START_ADDR() bfin_readPTR(MDMA_D3_START_ADDR)
#define bfin_write_MDMA_D3_START_ADDR(val) bfin_writePTR(MDMA_D3_START_ADDR, val)
#define pMDMA_D3_CONFIG                ((uint16_t volatile *)MDMA_D3_CONFIG) /* Memory DMA Stream 3 Destination Configuration Register */
#define bfin_read_MDMA_D3_CONFIG()     bfin_read16(MDMA_D3_CONFIG)
#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
#define pMDMA_D3_X_COUNT               ((uint16_t volatile *)MDMA_D3_X_COUNT) /* Memory DMA Stream 3 Destination X Count Register */
#define bfin_read_MDMA_D3_X_COUNT()    bfin_read16(MDMA_D3_X_COUNT)
#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
#define pMDMA_D3_X_MODIFY              ((uint16_t volatile *)MDMA_D3_X_MODIFY) /* Memory DMA Stream 3 Destination X Modify Register */
#define bfin_read_MDMA_D3_X_MODIFY()   bfin_read16(MDMA_D3_X_MODIFY)
#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY, val)
#define pMDMA_D3_Y_COUNT               ((uint16_t volatile *)MDMA_D3_Y_COUNT) /* Memory DMA Stream 3 Destination Y Count Register */
#define bfin_read_MDMA_D3_Y_COUNT()    bfin_read16(MDMA_D3_Y_COUNT)
#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
#define pMDMA_D3_Y_MODIFY              ((uint16_t volatile *)MDMA_D3_Y_MODIFY) /* Memory DMA Stream 3 Destination Y Modify Register */
#define bfin_read_MDMA_D3_Y_MODIFY()   bfin_read16(MDMA_D3_Y_MODIFY)
#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY, val)
#define pMDMA_D3_CURR_DESC_PTR         ((void * volatile *)MDMA_D3_CURR_DESC_PTR) /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_readPTR(MDMA_D3_CURR_DESC_PTR)
#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D3_CURR_DESC_PTR, val)
#define pMDMA_D3_CURR_ADDR             ((void * volatile *)MDMA_D3_CURR_ADDR) /* Memory DMA Stream 3 Destination Current Address Register */
#define bfin_read_MDMA_D3_CURR_ADDR()  bfin_readPTR(MDMA_D3_CURR_ADDR)
#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_writePTR(MDMA_D3_CURR_ADDR, val)
#define pMDMA_D3_IRQ_STATUS            ((uint16_t volatile *)MDMA_D3_IRQ_STATUS) /* Memory DMA Stream 3 Destination Interrupt/Status Register */
#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
#define pMDMA_D3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_D3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Destination Peripheral Map Register */
#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
#define pMDMA_D3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_X_COUNT) /* Memory DMA Stream 3 Destination Current X Count Register */
#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
#define pMDMA_D3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_D3_CURR_Y_COUNT) /* Memory DMA Stream 3 Destination Current Y Count Register */
#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
#define pMDMA_S3_NEXT_DESC_PTR         ((void * volatile *)MDMA_S3_NEXT_DESC_PTR) /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_readPTR(MDMA_S3_NEXT_DESC_PTR)
#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S3_NEXT_DESC_PTR, val)
#define pMDMA_S3_START_ADDR            ((void * volatile *)MDMA_S3_START_ADDR) /* Memory DMA Stream 3 Source Start Address Register */
#define bfin_read_MDMA_S3_START_ADDR() bfin_readPTR(MDMA_S3_START_ADDR)
#define bfin_write_MDMA_S3_START_ADDR(val) bfin_writePTR(MDMA_S3_START_ADDR, val)
#define pMDMA_S3_CONFIG                ((uint16_t volatile *)MDMA_S3_CONFIG) /* Memory DMA Stream 3 Source Configuration Register */
#define bfin_read_MDMA_S3_CONFIG()     bfin_read16(MDMA_S3_CONFIG)
#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
#define pMDMA_S3_X_COUNT               ((uint16_t volatile *)MDMA_S3_X_COUNT) /* Memory DMA Stream 3 Source X Count Register */
#define bfin_read_MDMA_S3_X_COUNT()    bfin_read16(MDMA_S3_X_COUNT)
#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
#define pMDMA_S3_X_MODIFY              ((uint16_t volatile *)MDMA_S3_X_MODIFY) /* Memory DMA Stream 3 Source X Modify Register */
#define bfin_read_MDMA_S3_X_MODIFY()   bfin_read16(MDMA_S3_X_MODIFY)
#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY, val)
#define pMDMA_S3_Y_COUNT               ((uint16_t volatile *)MDMA_S3_Y_COUNT) /* Memory DMA Stream 3 Source Y Count Register */
#define bfin_read_MDMA_S3_Y_COUNT()    bfin_read16(MDMA_S3_Y_COUNT)
#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
#define pMDMA_S3_Y_MODIFY              ((uint16_t volatile *)MDMA_S3_Y_MODIFY) /* Memory DMA Stream 3 Source Y Modify Register */
#define bfin_read_MDMA_S3_Y_MODIFY()   bfin_read16(MDMA_S3_Y_MODIFY)
#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY, val)
#define pMDMA_S3_CURR_DESC_PTR         ((void * volatile *)MDMA_S3_CURR_DESC_PTR) /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_readPTR(MDMA_S3_CURR_DESC_PTR)
#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S3_CURR_DESC_PTR, val)
#define pMDMA_S3_CURR_ADDR             ((void * volatile *)MDMA_S3_CURR_ADDR) /* Memory DMA Stream 3 Source Current Address Register */
#define bfin_read_MDMA_S3_CURR_ADDR()  bfin_readPTR(MDMA_S3_CURR_ADDR)
#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_writePTR(MDMA_S3_CURR_ADDR, val)
#define pMDMA_S3_IRQ_STATUS            ((uint16_t volatile *)MDMA_S3_IRQ_STATUS) /* Memory DMA Stream 3 Source Interrupt/Status Register */
#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
#define pMDMA_S3_PERIPHERAL_MAP        ((uint16_t volatile *)MDMA_S3_PERIPHERAL_MAP) /* Memory DMA Stream 3 Source Peripheral Map Register */
#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
#define pMDMA_S3_CURR_X_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_X_COUNT) /* Memory DMA Stream 3 Source Current X Count Register */
#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
#define pMDMA_S3_CURR_Y_COUNT          ((uint16_t volatile *)MDMA_S3_CURR_Y_COUNT) /* Memory DMA Stream 3 Source Current Y Count Register */
#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
#define pHMDMA0_CONTROL                ((uint16_t volatile *)HMDMA0_CONTROL) /* Handshake MDMA0 Control Register */
#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
#define pHMDMA0_ECINIT                 ((uint16_t volatile *)HMDMA0_ECINIT) /* Handshake MDMA0 Initial Edge Count Register */
#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
#define pHMDMA0_BCINIT                 ((uint16_t volatile *)HMDMA0_BCINIT) /* Handshake MDMA0 Initial Block Count Register */
#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
#define pHMDMA0_ECOUNT                 ((uint16_t volatile *)HMDMA0_ECOUNT) /* Handshake MDMA0 Current Edge Count Register */
#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
#define pHMDMA0_BCOUNT                 ((uint16_t volatile *)HMDMA0_BCOUNT) /* Handshake MDMA0 Current Block Count Register */
#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
#define pHMDMA0_ECURGENT               ((uint16_t volatile *)HMDMA0_ECURGENT) /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
#define pHMDMA0_ECOVERFLOW             ((uint16_t volatile *)HMDMA0_ECOVERFLOW) /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
#define pHMDMA1_CONTROL                ((uint16_t volatile *)HMDMA1_CONTROL) /* Handshake MDMA1 Control Register */
#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
#define pHMDMA1_ECINIT                 ((uint16_t volatile *)HMDMA1_ECINIT) /* Handshake MDMA1 Initial Edge Count Register */
#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
#define pHMDMA1_BCINIT                 ((uint16_t volatile *)HMDMA1_BCINIT) /* Handshake MDMA1 Initial Block Count Register */
#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
#define pHMDMA1_ECURGENT               ((uint16_t volatile *)HMDMA1_ECURGENT) /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
#define pHMDMA1_ECOVERFLOW             ((uint16_t volatile *)HMDMA1_ECOVERFLOW) /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
#define pHMDMA1_ECOUNT                 ((uint16_t volatile *)HMDMA1_ECOUNT) /* Handshake MDMA1 Current Edge Count Register */
#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
#define pHMDMA1_BCOUNT                 ((uint16_t volatile *)HMDMA1_BCOUNT) /* Handshake MDMA1 Current Block Count Register */
#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL) /* Asynchronous Memory Global Control Register */
#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1) /* Asynchronous Memory Bank Control Register */
#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
#define pEBIU_MBSCTL                   ((uint32_t volatile *)EBIU_MBSCTL) /* Asynchronous Memory Bank Select Control Register */
#define bfin_read_EBIU_MBSCTL()        bfin_read32(EBIU_MBSCTL)
#define bfin_write_EBIU_MBSCTL(val)    bfin_write32(EBIU_MBSCTL, val)
#define pEBIU_ARBSTAT                  ((uint32_t volatile *)EBIU_ARBSTAT) /* Asynchronous Memory Arbiter Status Register */
#define bfin_read_EBIU_ARBSTAT()       bfin_read32(EBIU_ARBSTAT)
#define bfin_write_EBIU_ARBSTAT(val)   bfin_write32(EBIU_ARBSTAT, val)
#define pEBIU_MODE                     ((uint32_t volatile *)EBIU_MODE) /* Asynchronous Mode Control Register */
#define bfin_read_EBIU_MODE()          bfin_read32(EBIU_MODE)
#define bfin_write_EBIU_MODE(val)      bfin_write32(EBIU_MODE, val)
#define pEBIU_FCTL                     ((uint32_t volatile *)EBIU_FCTL) /* Asynchronous Memory Flash Control Register */
#define bfin_read_EBIU_FCTL()          bfin_read32(EBIU_FCTL)
#define bfin_write_EBIU_FCTL(val)      bfin_write32(EBIU_FCTL, val)
#define pEBIU_DDRCTL0                  ((uint32_t volatile *)EBIU_DDRCTL0) /* DDR Memory Control 0 Register */
#define bfin_read_EBIU_DDRCTL0()       bfin_read32(EBIU_DDRCTL0)
#define bfin_write_EBIU_DDRCTL0(val)   bfin_write32(EBIU_DDRCTL0, val)
#define pEBIU_DDRCTL1                  ((uint32_t volatile *)EBIU_DDRCTL1) /* DDR Memory Control 1 Register */
#define bfin_read_EBIU_DDRCTL1()       bfin_read32(EBIU_DDRCTL1)
#define bfin_write_EBIU_DDRCTL1(val)   bfin_write32(EBIU_DDRCTL1, val)
#define pEBIU_DDRCTL2                  ((uint32_t volatile *)EBIU_DDRCTL2) /* DDR Memory Control 2 Register */
#define bfin_read_EBIU_DDRCTL2()       bfin_read32(EBIU_DDRCTL2)
#define bfin_write_EBIU_DDRCTL2(val)   bfin_write32(EBIU_DDRCTL2, val)
#define pEBIU_DDRCTL3                  ((uint32_t volatile *)EBIU_DDRCTL3) /* DDR Memory Control 3 Register */
#define bfin_read_EBIU_DDRCTL3()       bfin_read32(EBIU_DDRCTL3)
#define bfin_write_EBIU_DDRCTL3(val)   bfin_write32(EBIU_DDRCTL3, val)
#define pEBIU_DDRQUE                   ((uint32_t volatile *)EBIU_DDRQUE) /* DDR Queue Configuration Register */
#define bfin_read_EBIU_DDRQUE()        bfin_read32(EBIU_DDRQUE)
#define bfin_write_EBIU_DDRQUE(val)    bfin_write32(EBIU_DDRQUE, val)
#define pEBIU_ERRADD                   ((void * volatile *)EBIU_ERRADD) /* DDR Error Address Register */
#define bfin_read_EBIU_ERRADD()        bfin_readPTR(EBIU_ERRADD)
#define bfin_write_EBIU_ERRADD(val)    bfin_writePTR(EBIU_ERRADD, val)
#define pEBIU_ERRMST                   ((uint16_t volatile *)EBIU_ERRMST) /* DDR Error Master Register */
#define bfin_read_EBIU_ERRMST()        bfin_read16(EBIU_ERRMST)
#define bfin_write_EBIU_ERRMST(val)    bfin_write16(EBIU_ERRMST, val)
#define pEBIU_RSTCTL                   ((uint16_t volatile *)EBIU_RSTCTL) /* DDR Reset Control Register */
#define bfin_read_EBIU_RSTCTL()        bfin_read16(EBIU_RSTCTL)
#define bfin_write_EBIU_RSTCTL(val)    bfin_write16(EBIU_RSTCTL, val)
#define pEBIU_DDRBRC0                  ((uint32_t volatile *)EBIU_DDRBRC0) /* DDR Bank0 Read Count Register */
#define bfin_read_EBIU_DDRBRC0()       bfin_read32(EBIU_DDRBRC0)
#define bfin_write_EBIU_DDRBRC0(val)   bfin_write32(EBIU_DDRBRC0, val)
#define pEBIU_DDRBRC1                  ((uint32_t volatile *)EBIU_DDRBRC1) /* DDR Bank1 Read Count Register */
#define bfin_read_EBIU_DDRBRC1()       bfin_read32(EBIU_DDRBRC1)
#define bfin_write_EBIU_DDRBRC1(val)   bfin_write32(EBIU_DDRBRC1, val)
#define pEBIU_DDRBRC2                  ((uint32_t volatile *)EBIU_DDRBRC2) /* DDR Bank2 Read Count Register */
#define bfin_read_EBIU_DDRBRC2()       bfin_read32(EBIU_DDRBRC2)
#define bfin_write_EBIU_DDRBRC2(val)   bfin_write32(EBIU_DDRBRC2, val)
#define pEBIU_DDRBRC3                  ((uint32_t volatile *)EBIU_DDRBRC3) /* DDR Bank3 Read Count Register */
#define bfin_read_EBIU_DDRBRC3()       bfin_read32(EBIU_DDRBRC3)
#define bfin_write_EBIU_DDRBRC3(val)   bfin_write32(EBIU_DDRBRC3, val)
#define pEBIU_DDRBRC4                  ((uint32_t volatile *)EBIU_DDRBRC4) /* DDR Bank4 Read Count Register */
#define bfin_read_EBIU_DDRBRC4()       bfin_read32(EBIU_DDRBRC4)
#define bfin_write_EBIU_DDRBRC4(val)   bfin_write32(EBIU_DDRBRC4, val)
#define pEBIU_DDRBRC5                  ((uint32_t volatile *)EBIU_DDRBRC5) /* DDR Bank5 Read Count Register */
#define bfin_read_EBIU_DDRBRC5()       bfin_read32(EBIU_DDRBRC5)
#define bfin_write_EBIU_DDRBRC5(val)   bfin_write32(EBIU_DDRBRC5, val)
#define pEBIU_DDRBRC6                  ((uint32_t volatile *)EBIU_DDRBRC6) /* DDR Bank6 Read Count Register */
#define bfin_read_EBIU_DDRBRC6()       bfin_read32(EBIU_DDRBRC6)
#define bfin_write_EBIU_DDRBRC6(val)   bfin_write32(EBIU_DDRBRC6, val)
#define pEBIU_DDRBRC7                  ((uint32_t volatile *)EBIU_DDRBRC7) /* DDR Bank7 Read Count Register */
#define bfin_read_EBIU_DDRBRC7()       bfin_read32(EBIU_DDRBRC7)
#define bfin_write_EBIU_DDRBRC7(val)   bfin_write32(EBIU_DDRBRC7, val)
#define pEBIU_DDRBWC0                  ((uint32_t volatile *)EBIU_DDRBWC0) /* DDR Bank0 Write Count Register */
#define bfin_read_EBIU_DDRBWC0()       bfin_read32(EBIU_DDRBWC0)
#define bfin_write_EBIU_DDRBWC0(val)   bfin_write32(EBIU_DDRBWC0, val)
#define pEBIU_DDRBWC1                  ((uint32_t volatile *)EBIU_DDRBWC1) /* DDR Bank1 Write Count Register */
#define bfin_read_EBIU_DDRBWC1()       bfin_read32(EBIU_DDRBWC1)
#define bfin_write_EBIU_DDRBWC1(val)   bfin_write32(EBIU_DDRBWC1, val)
#define pEBIU_DDRBWC2                  ((uint32_t volatile *)EBIU_DDRBWC2) /* DDR Bank2 Write Count Register */
#define bfin_read_EBIU_DDRBWC2()       bfin_read32(EBIU_DDRBWC2)
#define bfin_write_EBIU_DDRBWC2(val)   bfin_write32(EBIU_DDRBWC2, val)
#define pEBIU_DDRBWC3                  ((uint32_t volatile *)EBIU_DDRBWC3) /* DDR Bank3 Write Count Register */
#define bfin_read_EBIU_DDRBWC3()       bfin_read32(EBIU_DDRBWC3)
#define bfin_write_EBIU_DDRBWC3(val)   bfin_write32(EBIU_DDRBWC3, val)
#define pEBIU_DDRBWC4                  ((uint32_t volatile *)EBIU_DDRBWC4) /* DDR Bank4 Write Count Register */
#define bfin_read_EBIU_DDRBWC4()       bfin_read32(EBIU_DDRBWC4)
#define bfin_write_EBIU_DDRBWC4(val)   bfin_write32(EBIU_DDRBWC4, val)
#define pEBIU_DDRBWC5                  ((uint32_t volatile *)EBIU_DDRBWC5) /* DDR Bank5 Write Count Register */
#define bfin_read_EBIU_DDRBWC5()       bfin_read32(EBIU_DDRBWC5)
#define bfin_write_EBIU_DDRBWC5(val)   bfin_write32(EBIU_DDRBWC5, val)
#define pEBIU_DDRBWC6                  ((uint32_t volatile *)EBIU_DDRBWC6) /* DDR Bank6 Write Count Register */
#define bfin_read_EBIU_DDRBWC6()       bfin_read32(EBIU_DDRBWC6)
#define bfin_write_EBIU_DDRBWC6(val)   bfin_write32(EBIU_DDRBWC6, val)
#define pEBIU_DDRBWC7                  ((uint32_t volatile *)EBIU_DDRBWC7) /* DDR Bank7 Write Count Register */
#define bfin_read_EBIU_DDRBWC7()       bfin_read32(EBIU_DDRBWC7)
#define bfin_write_EBIU_DDRBWC7(val)   bfin_write32(EBIU_DDRBWC7, val)
#define pEBIU_DDRACCT                  ((uint32_t volatile *)EBIU_DDRACCT) /* DDR Activation Count Register */
#define bfin_read_EBIU_DDRACCT()       bfin_read32(EBIU_DDRACCT)
#define bfin_write_EBIU_DDRACCT(val)   bfin_write32(EBIU_DDRACCT, val)
#define pEBIU_DDRTACT                  ((uint32_t volatile *)EBIU_DDRTACT) /* DDR Turn Around Count Register */
#define bfin_read_EBIU_DDRTACT()       bfin_read32(EBIU_DDRTACT)
#define bfin_write_EBIU_DDRTACT(val)   bfin_write32(EBIU_DDRTACT, val)
#define pEBIU_DDRARCT                  ((uint32_t volatile *)EBIU_DDRARCT) /* DDR Auto-refresh Count Register */
#define bfin_read_EBIU_DDRARCT()       bfin_read32(EBIU_DDRARCT)
#define bfin_write_EBIU_DDRARCT(val)   bfin_write32(EBIU_DDRARCT, val)
#define pEBIU_DDRGC0                   ((uint32_t volatile *)EBIU_DDRGC0) /* DDR Grant Count 0 Register */
#define bfin_read_EBIU_DDRGC0()        bfin_read32(EBIU_DDRGC0)
#define bfin_write_EBIU_DDRGC0(val)    bfin_write32(EBIU_DDRGC0, val)
#define pEBIU_DDRGC1                   ((uint32_t volatile *)EBIU_DDRGC1) /* DDR Grant Count 1 Register */
#define bfin_read_EBIU_DDRGC1()        bfin_read32(EBIU_DDRGC1)
#define bfin_write_EBIU_DDRGC1(val)    bfin_write32(EBIU_DDRGC1, val)
#define pEBIU_DDRGC2                   ((uint32_t volatile *)EBIU_DDRGC2) /* DDR Grant Count 2 Register */
#define bfin_read_EBIU_DDRGC2()        bfin_read32(EBIU_DDRGC2)
#define bfin_write_EBIU_DDRGC2(val)    bfin_write32(EBIU_DDRGC2, val)
#define pEBIU_DDRGC3                   ((uint32_t volatile *)EBIU_DDRGC3) /* DDR Grant Count 3 Register */
#define bfin_read_EBIU_DDRGC3()        bfin_read32(EBIU_DDRGC3)
#define bfin_write_EBIU_DDRGC3(val)    bfin_write32(EBIU_DDRGC3, val)
#define pEBIU_DDRMCEN                  ((uint32_t volatile *)EBIU_DDRMCEN) /* DDR Metrics Counter Enable Register */
#define bfin_read_EBIU_DDRMCEN()       bfin_read32(EBIU_DDRMCEN)
#define bfin_write_EBIU_DDRMCEN(val)   bfin_write32(EBIU_DDRMCEN, val)
#define pEBIU_DDRMCCL                  ((uint32_t volatile *)EBIU_DDRMCCL) /* DDR Metrics Counter Clear Register */
#define bfin_read_EBIU_DDRMCCL()       bfin_read32(EBIU_DDRMCCL)
#define bfin_write_EBIU_DDRMCCL(val)   bfin_write32(EBIU_DDRMCCL, val)
#define pPIXC_CTL                      ((uint16_t volatile *)PIXC_CTL) /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
#define bfin_read_PIXC_CTL()           bfin_read16(PIXC_CTL)
#define bfin_write_PIXC_CTL(val)       bfin_write16(PIXC_CTL, val)
#define pPIXC_PPL                      ((uint16_t volatile *)PIXC_PPL) /* Holds the number of pixels per line of the display */
#define bfin_read_PIXC_PPL()           bfin_read16(PIXC_PPL)
#define bfin_write_PIXC_PPL(val)       bfin_write16(PIXC_PPL, val)
#define pPIXC_LPF                      ((uint16_t volatile *)PIXC_LPF) /* Holds the number of lines per frame of the display */
#define bfin_read_PIXC_LPF()           bfin_read16(PIXC_LPF)
#define bfin_write_PIXC_LPF(val)       bfin_write16(PIXC_LPF, val)
#define pPIXC_AHSTART                  ((uint16_t volatile *)PIXC_AHSTART) /* Contains horizontal start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHSTART()       bfin_read16(PIXC_AHSTART)
#define bfin_write_PIXC_AHSTART(val)   bfin_write16(PIXC_AHSTART, val)
#define pPIXC_AHEND                    ((uint16_t volatile *)PIXC_AHEND) /* Contains horizontal end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AHEND()         bfin_read16(PIXC_AHEND)
#define bfin_write_PIXC_AHEND(val)     bfin_write16(PIXC_AHEND, val)
#define pPIXC_AVSTART                  ((uint16_t volatile *)PIXC_AVSTART) /* Contains vertical start pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVSTART()       bfin_read16(PIXC_AVSTART)
#define bfin_write_PIXC_AVSTART(val)   bfin_write16(PIXC_AVSTART, val)
#define pPIXC_AVEND                    ((uint16_t volatile *)PIXC_AVEND) /* Contains vertical end pixel information of the overlay data (set A) */
#define bfin_read_PIXC_AVEND()         bfin_read16(PIXC_AVEND)
#define bfin_write_PIXC_AVEND(val)     bfin_write16(PIXC_AVEND, val)
#define pPIXC_ATRANSP                  ((uint16_t volatile *)PIXC_ATRANSP) /* Contains the transparency ratio (set A) */
#define bfin_read_PIXC_ATRANSP()       bfin_read16(PIXC_ATRANSP)
#define bfin_write_PIXC_ATRANSP(val)   bfin_write16(PIXC_ATRANSP, val)
#define pPIXC_BHSTART                  ((uint16_t volatile *)PIXC_BHSTART) /* Contains horizontal start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHSTART()       bfin_read16(PIXC_BHSTART)
#define bfin_write_PIXC_BHSTART(val)   bfin_write16(PIXC_BHSTART, val)
#define pPIXC_BHEND                    ((uint16_t volatile *)PIXC_BHEND) /* Contains horizontal end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BHEND()         bfin_read16(PIXC_BHEND)
#define bfin_write_PIXC_BHEND(val)     bfin_write16(PIXC_BHEND, val)
#define pPIXC_BVSTART                  ((uint16_t volatile *)PIXC_BVSTART) /* Contains vertical start pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVSTART()       bfin_read16(PIXC_BVSTART)
#define bfin_write_PIXC_BVSTART(val)   bfin_write16(PIXC_BVSTART, val)
#define pPIXC_BVEND                    ((uint16_t volatile *)PIXC_BVEND) /* Contains vertical end pixel information of the overlay data (set B) */
#define bfin_read_PIXC_BVEND()         bfin_read16(PIXC_BVEND)
#define bfin_write_PIXC_BVEND(val)     bfin_write16(PIXC_BVEND, val)
#define pPIXC_BTRANSP                  ((uint16_t volatile *)PIXC_BTRANSP) /* Contains the transparency ratio (set B) */
#define bfin_read_PIXC_BTRANSP()       bfin_read16(PIXC_BTRANSP)
#define bfin_write_PIXC_BTRANSP(val)   bfin_write16(PIXC_BTRANSP, val)
#define pPIXC_INTRSTAT                 ((uint16_t volatile *)PIXC_INTRSTAT) /* Overlay interrupt configuration/status */
#define bfin_read_PIXC_INTRSTAT()      bfin_read16(PIXC_INTRSTAT)
#define bfin_write_PIXC_INTRSTAT(val)  bfin_write16(PIXC_INTRSTAT, val)
#define pPIXC_RYCON                    ((uint32_t volatile *)PIXC_RYCON) /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
#define bfin_read_PIXC_RYCON()         bfin_read32(PIXC_RYCON)
#define bfin_write_PIXC_RYCON(val)     bfin_write32(PIXC_RYCON, val)
#define pPIXC_GUCON                    ((uint32_t volatile *)PIXC_GUCON) /* Color space conversion matrix register. Contains the G/U conversion coefficients */
#define bfin_read_PIXC_GUCON()         bfin_read32(PIXC_GUCON)
#define bfin_write_PIXC_GUCON(val)     bfin_write32(PIXC_GUCON, val)
#define pPIXC_BVCON                    ((uint32_t volatile *)PIXC_BVCON) /* Color space conversion matrix register. Contains the B/V conversion coefficients */
#define bfin_read_PIXC_BVCON()         bfin_read32(PIXC_BVCON)
#define bfin_write_PIXC_BVCON(val)     bfin_write32(PIXC_BVCON, val)
#define pPIXC_CCBIAS                   ((uint32_t volatile *)PIXC_CCBIAS) /* Bias values for the color space conversion matrix */
#define bfin_read_PIXC_CCBIAS()        bfin_read32(PIXC_CCBIAS)
#define bfin_write_PIXC_CCBIAS(val)    bfin_write32(PIXC_CCBIAS, val)
#define pPIXC_TC                       ((uint32_t volatile *)PIXC_TC) /* Holds the transparent color value */
#define bfin_read_PIXC_TC()            bfin_read32(PIXC_TC)
#define bfin_write_PIXC_TC(val)        bfin_write32(PIXC_TC, val)
#define pHOST_CONTROL                  ((uint16_t volatile *)HOST_CONTROL) /* HOSTDP Control Register */
#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
#define pHOST_STATUS                   ((uint16_t volatile *)HOST_STATUS) /* HOSTDP Status Register */
#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
#define pHOST_TIMEOUT                  ((uint16_t volatile *)HOST_TIMEOUT) /* HOSTDP Acknowledge Mode Timeout Register */
#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
#define pPORTA_FER                     ((uint16_t volatile *)PORTA_FER) /* Function Enable Register */
#define bfin_read_PORTA_FER()          bfin_read16(PORTA_FER)
#define bfin_write_PORTA_FER(val)      bfin_write16(PORTA_FER, val)
#define pPORTA                         ((uint16_t volatile *)PORTA) /* GPIO Data Register */
#define bfin_read_PORTA()              bfin_read16(PORTA)
#define bfin_write_PORTA(val)          bfin_write16(PORTA, val)
#define pPORTA_SET                     ((uint16_t volatile *)PORTA_SET) /* GPIO Data Set Register */
#define bfin_read_PORTA_SET()          bfin_read16(PORTA_SET)
#define bfin_write_PORTA_SET(val)      bfin_write16(PORTA_SET, val)
#define pPORTA_CLEAR                   ((uint16_t volatile *)PORTA_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTA_CLEAR()        bfin_read16(PORTA_CLEAR)
#define bfin_write_PORTA_CLEAR(val)    bfin_write16(PORTA_CLEAR, val)
#define pPORTA_DIR_SET                 ((uint16_t volatile *)PORTA_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTA_DIR_SET()      bfin_read16(PORTA_DIR_SET)
#define bfin_write_PORTA_DIR_SET(val)  bfin_write16(PORTA_DIR_SET, val)
#define pPORTA_DIR_CLEAR               ((uint16_t volatile *)PORTA_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTA_DIR_CLEAR()    bfin_read16(PORTA_DIR_CLEAR)
#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
#define pPORTA_INEN                    ((uint16_t volatile *)PORTA_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTA_INEN()         bfin_read16(PORTA_INEN)
#define bfin_write_PORTA_INEN(val)     bfin_write16(PORTA_INEN, val)
#define pPORTA_MUX                     ((uint32_t volatile *)PORTA_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTA_MUX()          bfin_read32(PORTA_MUX)
#define bfin_write_PORTA_MUX(val)      bfin_write32(PORTA_MUX, val)
#define pPORTB_FER                     ((uint16_t volatile *)PORTB_FER) /* Function Enable Register */
#define bfin_read_PORTB_FER()          bfin_read16(PORTB_FER)
#define bfin_write_PORTB_FER(val)      bfin_write16(PORTB_FER, val)
#define pPORTB                         ((uint16_t volatile *)PORTB) /* GPIO Data Register */
#define bfin_read_PORTB()              bfin_read16(PORTB)
#define bfin_write_PORTB(val)          bfin_write16(PORTB, val)
#define pPORTB_SET                     ((uint16_t volatile *)PORTB_SET) /* GPIO Data Set Register */
#define bfin_read_PORTB_SET()          bfin_read16(PORTB_SET)
#define bfin_write_PORTB_SET(val)      bfin_write16(PORTB_SET, val)
#define pPORTB_CLEAR                   ((uint16_t volatile *)PORTB_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTB_CLEAR()        bfin_read16(PORTB_CLEAR)
#define bfin_write_PORTB_CLEAR(val)    bfin_write16(PORTB_CLEAR, val)
#define pPORTB_DIR_SET                 ((uint16_t volatile *)PORTB_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTB_DIR_SET()      bfin_read16(PORTB_DIR_SET)
#define bfin_write_PORTB_DIR_SET(val)  bfin_write16(PORTB_DIR_SET, val)
#define pPORTB_DIR_CLEAR               ((uint16_t volatile *)PORTB_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTB_DIR_CLEAR()    bfin_read16(PORTB_DIR_CLEAR)
#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
#define pPORTB_INEN                    ((uint16_t volatile *)PORTB_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTB_INEN()         bfin_read16(PORTB_INEN)
#define bfin_write_PORTB_INEN(val)     bfin_write16(PORTB_INEN, val)
#define pPORTB_MUX                     ((uint32_t volatile *)PORTB_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTB_MUX()          bfin_read32(PORTB_MUX)
#define bfin_write_PORTB_MUX(val)      bfin_write32(PORTB_MUX, val)
#define pPORTC_FER                     ((uint16_t volatile *)PORTC_FER) /* Function Enable Register */
#define bfin_read_PORTC_FER()          bfin_read16(PORTC_FER)
#define bfin_write_PORTC_FER(val)      bfin_write16(PORTC_FER, val)
#define pPORTC                         ((uint16_t volatile *)PORTC) /* GPIO Data Register */
#define bfin_read_PORTC()              bfin_read16(PORTC)
#define bfin_write_PORTC(val)          bfin_write16(PORTC, val)
#define pPORTC_SET                     ((uint16_t volatile *)PORTC_SET) /* GPIO Data Set Register */
#define bfin_read_PORTC_SET()          bfin_read16(PORTC_SET)
#define bfin_write_PORTC_SET(val)      bfin_write16(PORTC_SET, val)
#define pPORTC_CLEAR                   ((uint16_t volatile *)PORTC_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTC_CLEAR()        bfin_read16(PORTC_CLEAR)
#define bfin_write_PORTC_CLEAR(val)    bfin_write16(PORTC_CLEAR, val)
#define pPORTC_DIR_SET                 ((uint16_t volatile *)PORTC_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTC_DIR_SET()      bfin_read16(PORTC_DIR_SET)
#define bfin_write_PORTC_DIR_SET(val)  bfin_write16(PORTC_DIR_SET, val)
#define pPORTC_DIR_CLEAR               ((uint16_t volatile *)PORTC_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTC_DIR_CLEAR()    bfin_read16(PORTC_DIR_CLEAR)
#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
#define pPORTC_INEN                    ((uint16_t volatile *)PORTC_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTC_INEN()         bfin_read16(PORTC_INEN)
#define bfin_write_PORTC_INEN(val)     bfin_write16(PORTC_INEN, val)
#define pPORTC_MUX                     ((uint32_t volatile *)PORTC_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTC_MUX()          bfin_read32(PORTC_MUX)
#define bfin_write_PORTC_MUX(val)      bfin_write32(PORTC_MUX, val)
#define pPORTD_FER                     ((uint16_t volatile *)PORTD_FER) /* Function Enable Register */
#define bfin_read_PORTD_FER()          bfin_read16(PORTD_FER)
#define bfin_write_PORTD_FER(val)      bfin_write16(PORTD_FER, val)
#define pPORTD                         ((uint16_t volatile *)PORTD) /* GPIO Data Register */
#define bfin_read_PORTD()              bfin_read16(PORTD)
#define bfin_write_PORTD(val)          bfin_write16(PORTD, val)
#define pPORTD_SET                     ((uint16_t volatile *)PORTD_SET) /* GPIO Data Set Register */
#define bfin_read_PORTD_SET()          bfin_read16(PORTD_SET)
#define bfin_write_PORTD_SET(val)      bfin_write16(PORTD_SET, val)
#define pPORTD_CLEAR                   ((uint16_t volatile *)PORTD_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTD_CLEAR()        bfin_read16(PORTD_CLEAR)
#define bfin_write_PORTD_CLEAR(val)    bfin_write16(PORTD_CLEAR, val)
#define pPORTD_DIR_SET                 ((uint16_t volatile *)PORTD_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTD_DIR_SET()      bfin_read16(PORTD_DIR_SET)
#define bfin_write_PORTD_DIR_SET(val)  bfin_write16(PORTD_DIR_SET, val)
#define pPORTD_DIR_CLEAR               ((uint16_t volatile *)PORTD_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTD_DIR_CLEAR()    bfin_read16(PORTD_DIR_CLEAR)
#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
#define pPORTD_INEN                    ((uint16_t volatile *)PORTD_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTD_INEN()         bfin_read16(PORTD_INEN)
#define bfin_write_PORTD_INEN(val)     bfin_write16(PORTD_INEN, val)
#define pPORTD_MUX                     ((uint32_t volatile *)PORTD_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTD_MUX()          bfin_read32(PORTD_MUX)
#define bfin_write_PORTD_MUX(val)      bfin_write32(PORTD_MUX, val)
#define pPORTE_FER                     ((uint16_t volatile *)PORTE_FER) /* Function Enable Register */
#define bfin_read_PORTE_FER()          bfin_read16(PORTE_FER)
#define bfin_write_PORTE_FER(val)      bfin_write16(PORTE_FER, val)
#define pPORTE                         ((uint16_t volatile *)PORTE) /* GPIO Data Register */
#define bfin_read_PORTE()              bfin_read16(PORTE)
#define bfin_write_PORTE(val)          bfin_write16(PORTE, val)
#define pPORTE_SET                     ((uint16_t volatile *)PORTE_SET) /* GPIO Data Set Register */
#define bfin_read_PORTE_SET()          bfin_read16(PORTE_SET)
#define bfin_write_PORTE_SET(val)      bfin_write16(PORTE_SET, val)
#define pPORTE_CLEAR                   ((uint16_t volatile *)PORTE_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTE_CLEAR()        bfin_read16(PORTE_CLEAR)
#define bfin_write_PORTE_CLEAR(val)    bfin_write16(PORTE_CLEAR, val)
#define pPORTE_DIR_SET                 ((uint16_t volatile *)PORTE_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTE_DIR_SET()      bfin_read16(PORTE_DIR_SET)
#define bfin_write_PORTE_DIR_SET(val)  bfin_write16(PORTE_DIR_SET, val)
#define pPORTE_DIR_CLEAR               ((uint16_t volatile *)PORTE_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTE_DIR_CLEAR()    bfin_read16(PORTE_DIR_CLEAR)
#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
#define pPORTE_INEN                    ((uint16_t volatile *)PORTE_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTE_INEN()         bfin_read16(PORTE_INEN)
#define bfin_write_PORTE_INEN(val)     bfin_write16(PORTE_INEN, val)
#define pPORTE_MUX                     ((uint32_t volatile *)PORTE_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTE_MUX()          bfin_read32(PORTE_MUX)
#define bfin_write_PORTE_MUX(val)      bfin_write32(PORTE_MUX, val)
#define pPORTF_FER                     ((uint16_t volatile *)PORTF_FER) /* Function Enable Register */
#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
#define pPORTF                         ((uint16_t volatile *)PORTF) /* GPIO Data Register */
#define bfin_read_PORTF()              bfin_read16(PORTF)
#define bfin_write_PORTF(val)          bfin_write16(PORTF, val)
#define pPORTF_SET                     ((uint16_t volatile *)PORTF_SET) /* GPIO Data Set Register */
#define bfin_read_PORTF_SET()          bfin_read16(PORTF_SET)
#define bfin_write_PORTF_SET(val)      bfin_write16(PORTF_SET, val)
#define pPORTF_CLEAR                   ((uint16_t volatile *)PORTF_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTF_CLEAR()        bfin_read16(PORTF_CLEAR)
#define bfin_write_PORTF_CLEAR(val)    bfin_write16(PORTF_CLEAR, val)
#define pPORTF_DIR_SET                 ((uint16_t volatile *)PORTF_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTF_DIR_SET()      bfin_read16(PORTF_DIR_SET)
#define bfin_write_PORTF_DIR_SET(val)  bfin_write16(PORTF_DIR_SET, val)
#define pPORTF_DIR_CLEAR               ((uint16_t volatile *)PORTF_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTF_DIR_CLEAR()    bfin_read16(PORTF_DIR_CLEAR)
#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
#define pPORTF_INEN                    ((uint16_t volatile *)PORTF_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTF_INEN()         bfin_read16(PORTF_INEN)
#define bfin_write_PORTF_INEN(val)     bfin_write16(PORTF_INEN, val)
#define pPORTF_MUX                     ((uint32_t volatile *)PORTF_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTF_MUX()          bfin_read32(PORTF_MUX)
#define bfin_write_PORTF_MUX(val)      bfin_write32(PORTF_MUX, val)
#define pPORTG_FER                     ((uint16_t volatile *)PORTG_FER) /* Function Enable Register */
#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
#define pPORTG                         ((uint16_t volatile *)PORTG) /* GPIO Data Register */
#define bfin_read_PORTG()              bfin_read16(PORTG)
#define bfin_write_PORTG(val)          bfin_write16(PORTG, val)
#define pPORTG_SET                     ((uint16_t volatile *)PORTG_SET) /* GPIO Data Set Register */
#define bfin_read_PORTG_SET()          bfin_read16(PORTG_SET)
#define bfin_write_PORTG_SET(val)      bfin_write16(PORTG_SET, val)
#define pPORTG_CLEAR                   ((uint16_t volatile *)PORTG_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTG_CLEAR()        bfin_read16(PORTG_CLEAR)
#define bfin_write_PORTG_CLEAR(val)    bfin_write16(PORTG_CLEAR, val)
#define pPORTG_DIR_SET                 ((uint16_t volatile *)PORTG_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTG_DIR_SET()      bfin_read16(PORTG_DIR_SET)
#define bfin_write_PORTG_DIR_SET(val)  bfin_write16(PORTG_DIR_SET, val)
#define pPORTG_DIR_CLEAR               ((uint16_t volatile *)PORTG_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTG_DIR_CLEAR()    bfin_read16(PORTG_DIR_CLEAR)
#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
#define pPORTG_INEN                    ((uint16_t volatile *)PORTG_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTG_INEN()         bfin_read16(PORTG_INEN)
#define bfin_write_PORTG_INEN(val)     bfin_write16(PORTG_INEN, val)
#define pPORTG_MUX                     ((uint32_t volatile *)PORTG_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTG_MUX()          bfin_read32(PORTG_MUX)
#define bfin_write_PORTG_MUX(val)      bfin_write32(PORTG_MUX, val)
#define pPORTH_FER                     ((uint16_t volatile *)PORTH_FER) /* Function Enable Register */
#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
#define pPORTH                         ((uint16_t volatile *)PORTH) /* GPIO Data Register */
#define bfin_read_PORTH()              bfin_read16(PORTH)
#define bfin_write_PORTH(val)          bfin_write16(PORTH, val)
#define pPORTH_SET                     ((uint16_t volatile *)PORTH_SET) /* GPIO Data Set Register */
#define bfin_read_PORTH_SET()          bfin_read16(PORTH_SET)
#define bfin_write_PORTH_SET(val)      bfin_write16(PORTH_SET, val)
#define pPORTH_CLEAR                   ((uint16_t volatile *)PORTH_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTH_CLEAR()        bfin_read16(PORTH_CLEAR)
#define bfin_write_PORTH_CLEAR(val)    bfin_write16(PORTH_CLEAR, val)
#define pPORTH_DIR_SET                 ((uint16_t volatile *)PORTH_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTH_DIR_SET()      bfin_read16(PORTH_DIR_SET)
#define bfin_write_PORTH_DIR_SET(val)  bfin_write16(PORTH_DIR_SET, val)
#define pPORTH_DIR_CLEAR               ((uint16_t volatile *)PORTH_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTH_DIR_CLEAR()    bfin_read16(PORTH_DIR_CLEAR)
#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
#define pPORTH_INEN                    ((uint16_t volatile *)PORTH_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTH_INEN()         bfin_read16(PORTH_INEN)
#define bfin_write_PORTH_INEN(val)     bfin_write16(PORTH_INEN, val)
#define pPORTH_MUX                     ((uint32_t volatile *)PORTH_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTH_MUX()          bfin_read32(PORTH_MUX)
#define bfin_write_PORTH_MUX(val)      bfin_write32(PORTH_MUX, val)
#define pPORTI_FER                     ((uint16_t volatile *)PORTI_FER) /* Function Enable Register */
#define bfin_read_PORTI_FER()          bfin_read16(PORTI_FER)
#define bfin_write_PORTI_FER(val)      bfin_write16(PORTI_FER, val)
#define pPORTI                         ((uint16_t volatile *)PORTI) /* GPIO Data Register */
#define bfin_read_PORTI()              bfin_read16(PORTI)
#define bfin_write_PORTI(val)          bfin_write16(PORTI, val)
#define pPORTI_SET                     ((uint16_t volatile *)PORTI_SET) /* GPIO Data Set Register */
#define bfin_read_PORTI_SET()          bfin_read16(PORTI_SET)
#define bfin_write_PORTI_SET(val)      bfin_write16(PORTI_SET, val)
#define pPORTI_CLEAR                   ((uint16_t volatile *)PORTI_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTI_CLEAR()        bfin_read16(PORTI_CLEAR)
#define bfin_write_PORTI_CLEAR(val)    bfin_write16(PORTI_CLEAR, val)
#define pPORTI_DIR_SET                 ((uint16_t volatile *)PORTI_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTI_DIR_SET()      bfin_read16(PORTI_DIR_SET)
#define bfin_write_PORTI_DIR_SET(val)  bfin_write16(PORTI_DIR_SET, val)
#define pPORTI_DIR_CLEAR               ((uint16_t volatile *)PORTI_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTI_DIR_CLEAR()    bfin_read16(PORTI_DIR_CLEAR)
#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
#define pPORTI_INEN                    ((uint16_t volatile *)PORTI_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTI_INEN()         bfin_read16(PORTI_INEN)
#define bfin_write_PORTI_INEN(val)     bfin_write16(PORTI_INEN, val)
#define pPORTI_MUX                     ((uint32_t volatile *)PORTI_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTI_MUX()          bfin_read32(PORTI_MUX)
#define bfin_write_PORTI_MUX(val)      bfin_write32(PORTI_MUX, val)
#define pPORTJ_FER                     ((uint16_t volatile *)PORTJ_FER) /* Function Enable Register */
#define bfin_read_PORTJ_FER()          bfin_read16(PORTJ_FER)
#define bfin_write_PORTJ_FER(val)      bfin_write16(PORTJ_FER, val)
#define pPORTJ                         ((uint16_t volatile *)PORTJ) /* GPIO Data Register */
#define bfin_read_PORTJ()              bfin_read16(PORTJ)
#define bfin_write_PORTJ(val)          bfin_write16(PORTJ, val)
#define pPORTJ_SET                     ((uint16_t volatile *)PORTJ_SET) /* GPIO Data Set Register */
#define bfin_read_PORTJ_SET()          bfin_read16(PORTJ_SET)
#define bfin_write_PORTJ_SET(val)      bfin_write16(PORTJ_SET, val)
#define pPORTJ_CLEAR                   ((uint16_t volatile *)PORTJ_CLEAR) /* GPIO Data Clear Register */
#define bfin_read_PORTJ_CLEAR()        bfin_read16(PORTJ_CLEAR)
#define bfin_write_PORTJ_CLEAR(val)    bfin_write16(PORTJ_CLEAR, val)
#define pPORTJ_DIR_SET                 ((uint16_t volatile *)PORTJ_DIR_SET) /* GPIO Direction Set Register */
#define bfin_read_PORTJ_DIR_SET()      bfin_read16(PORTJ_DIR_SET)
#define bfin_write_PORTJ_DIR_SET(val)  bfin_write16(PORTJ_DIR_SET, val)
#define pPORTJ_DIR_CLEAR               ((uint16_t volatile *)PORTJ_DIR_CLEAR) /* GPIO Direction Clear Register */
#define bfin_read_PORTJ_DIR_CLEAR()    bfin_read16(PORTJ_DIR_CLEAR)
#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
#define pPORTJ_INEN                    ((uint16_t volatile *)PORTJ_INEN) /* GPIO Input Enable Register */
#define bfin_read_PORTJ_INEN()         bfin_read16(PORTJ_INEN)
#define bfin_write_PORTJ_INEN(val)     bfin_write16(PORTJ_INEN, val)
#define pPORTJ_MUX                     ((uint32_t volatile *)PORTJ_MUX) /* Multiplexer Control Register */
#define bfin_read_PORTJ_MUX()          bfin_read32(PORTJ_MUX)
#define bfin_write_PORTJ_MUX(val)      bfin_write32(PORTJ_MUX, val)
#define pPINT0_MASK_SET                ((uint32_t volatile *)PINT0_MASK_SET) /* Pin Interrupt 0 Mask Set Register */
#define bfin_read_PINT0_MASK_SET()     bfin_read32(PINT0_MASK_SET)
#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
#define pPINT0_MASK_CLEAR              ((uint32_t volatile *)PINT0_MASK_CLEAR) /* Pin Interrupt 0 Mask Clear Register */
#define bfin_read_PINT0_MASK_CLEAR()   bfin_read32(PINT0_MASK_CLEAR)
#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
#define pPINT0_IRQ                     ((uint32_t volatile *)PINT0_IRQ) /* Pin Interrupt 0 Interrupt Request Register */
#define bfin_read_PINT0_IRQ()          bfin_read32(PINT0_IRQ)
#define bfin_write_PINT0_IRQ(val)      bfin_write32(PINT0_IRQ, val)
#define pPINT0_ASSIGN                  ((uint32_t volatile *)PINT0_ASSIGN) /* Pin Interrupt 0 Port Assign Register */
#define bfin_read_PINT0_ASSIGN()       bfin_read32(PINT0_ASSIGN)
#define bfin_write_PINT0_ASSIGN(val)   bfin_write32(PINT0_ASSIGN, val)
#define pPINT0_EDGE_SET                ((uint32_t volatile *)PINT0_EDGE_SET) /* Pin Interrupt 0 Edge-sensitivity Set Register */
#define bfin_read_PINT0_EDGE_SET()     bfin_read32(PINT0_EDGE_SET)
#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
#define pPINT0_EDGE_CLEAR              ((uint32_t volatile *)PINT0_EDGE_CLEAR) /* Pin Interrupt 0 Edge-sensitivity Clear Register */
#define bfin_read_PINT0_EDGE_CLEAR()   bfin_read32(PINT0_EDGE_CLEAR)
#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
#define pPINT0_INVERT_SET              ((uint32_t volatile *)PINT0_INVERT_SET) /* Pin Interrupt 0 Inversion Set Register */
#define bfin_read_PINT0_INVERT_SET()   bfin_read32(PINT0_INVERT_SET)
#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
#define pPINT0_INVERT_CLEAR            ((uint32_t volatile *)PINT0_INVERT_CLEAR) /* Pin Interrupt 0 Inversion Clear Register */
#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
#define pPINT0_PINSTATE                ((uint32_t volatile *)PINT0_PINSTATE) /* Pin Interrupt 0 Pin Status Register */
#define bfin_read_PINT0_PINSTATE()     bfin_read32(PINT0_PINSTATE)
#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
#define pPINT0_LATCH                   ((uint32_t volatile *)PINT0_LATCH) /* Pin Interrupt 0 Latch Register */
#define bfin_read_PINT0_LATCH()        bfin_read32(PINT0_LATCH)
#define bfin_write_PINT0_LATCH(val)    bfin_write32(PINT0_LATCH, val)
#define pPINT1_MASK_SET                ((uint32_t volatile *)PINT1_MASK_SET) /* Pin Interrupt 1 Mask Set Register */
#define bfin_read_PINT1_MASK_SET()     bfin_read32(PINT1_MASK_SET)
#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
#define pPINT1_MASK_CLEAR              ((uint32_t volatile *)PINT1_MASK_CLEAR) /* Pin Interrupt 1 Mask Clear Register */
#define bfin_read_PINT1_MASK_CLEAR()   bfin_read32(PINT1_MASK_CLEAR)
#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
#define pPINT1_IRQ                     ((uint32_t volatile *)PINT1_IRQ) /* Pin Interrupt 1 Interrupt Request Register */
#define bfin_read_PINT1_IRQ()          bfin_read32(PINT1_IRQ)
#define bfin_write_PINT1_IRQ(val)      bfin_write32(PINT1_IRQ, val)
#define pPINT1_ASSIGN                  ((uint32_t volatile *)PINT1_ASSIGN) /* Pin Interrupt 1 Port Assign Register */
#define bfin_read_PINT1_ASSIGN()       bfin_read32(PINT1_ASSIGN)
#define bfin_write_PINT1_ASSIGN(val)   bfin_write32(PINT1_ASSIGN, val)
#define pPINT1_EDGE_SET                ((uint32_t volatile *)PINT1_EDGE_SET) /* Pin Interrupt 1 Edge-sensitivity Set Register */
#define bfin_read_PINT1_EDGE_SET()     bfin_read32(PINT1_EDGE_SET)
#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
#define pPINT1_EDGE_CLEAR              ((uint32_t volatile *)PINT1_EDGE_CLEAR) /* Pin Interrupt 1 Edge-sensitivity Clear Register */
#define bfin_read_PINT1_EDGE_CLEAR()   bfin_read32(PINT1_EDGE_CLEAR)
#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
#define pPINT1_INVERT_SET              ((uint32_t volatile *)PINT1_INVERT_SET) /* Pin Interrupt 1 Inversion Set Register */
#define bfin_read_PINT1_INVERT_SET()   bfin_read32(PINT1_INVERT_SET)
#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
#define pPINT1_INVERT_CLEAR            ((uint32_t volatile *)PINT1_INVERT_CLEAR) /* Pin Interrupt 1 Inversion Clear Register */
#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
#define pPINT1_PINSTATE                ((uint32_t volatile *)PINT1_PINSTATE) /* Pin Interrupt 1 Pin Status Register */
#define bfin_read_PINT1_PINSTATE()     bfin_read32(PINT1_PINSTATE)
#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
#define pPINT1_LATCH                   ((uint32_t volatile *)PINT1_LATCH) /* Pin Interrupt 1 Latch Register */
#define bfin_read_PINT1_LATCH()        bfin_read32(PINT1_LATCH)
#define bfin_write_PINT1_LATCH(val)    bfin_write32(PINT1_LATCH, val)
#define pPINT2_MASK_SET                ((uint32_t volatile *)PINT2_MASK_SET) /* Pin Interrupt 2 Mask Set Register */
#define bfin_read_PINT2_MASK_SET()     bfin_read32(PINT2_MASK_SET)
#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
#define pPINT2_MASK_CLEAR              ((uint32_t volatile *)PINT2_MASK_CLEAR) /* Pin Interrupt 2 Mask Clear Register */
#define bfin_read_PINT2_MASK_CLEAR()   bfin_read32(PINT2_MASK_CLEAR)
#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
#define pPINT2_IRQ                     ((uint32_t volatile *)PINT2_IRQ) /* Pin Interrupt 2 Interrupt Request Register */
#define bfin_read_PINT2_IRQ()          bfin_read32(PINT2_IRQ)
#define bfin_write_PINT2_IRQ(val)      bfin_write32(PINT2_IRQ, val)
#define pPINT2_ASSIGN                  ((uint32_t volatile *)PINT2_ASSIGN) /* Pin Interrupt 2 Port Assign Register */
#define bfin_read_PINT2_ASSIGN()       bfin_read32(PINT2_ASSIGN)
#define bfin_write_PINT2_ASSIGN(val)   bfin_write32(PINT2_ASSIGN, val)
#define pPINT2_EDGE_SET                ((uint32_t volatile *)PINT2_EDGE_SET) /* Pin Interrupt 2 Edge-sensitivity Set Register */
#define bfin_read_PINT2_EDGE_SET()     bfin_read32(PINT2_EDGE_SET)
#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
#define pPINT2_EDGE_CLEAR              ((uint32_t volatile *)PINT2_EDGE_CLEAR) /* Pin Interrupt 2 Edge-sensitivity Clear Register */
#define bfin_read_PINT2_EDGE_CLEAR()   bfin_read32(PINT2_EDGE_CLEAR)
#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
#define pPINT2_INVERT_SET              ((uint32_t volatile *)PINT2_INVERT_SET) /* Pin Interrupt 2 Inversion Set Register */
#define bfin_read_PINT2_INVERT_SET()   bfin_read32(PINT2_INVERT_SET)
#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
#define pPINT2_INVERT_CLEAR            ((uint32_t volatile *)PINT2_INVERT_CLEAR) /* Pin Interrupt 2 Inversion Clear Register */
#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
#define pPINT2_PINSTATE                ((uint32_t volatile *)PINT2_PINSTATE) /* Pin Interrupt 2 Pin Status Register */
#define bfin_read_PINT2_PINSTATE()     bfin_read32(PINT2_PINSTATE)
#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
#define pPINT2_LATCH                   ((uint32_t volatile *)PINT2_LATCH) /* Pin Interrupt 2 Latch Register */
#define bfin_read_PINT2_LATCH()        bfin_read32(PINT2_LATCH)
#define bfin_write_PINT2_LATCH(val)    bfin_write32(PINT2_LATCH, val)
#define pPINT3_MASK_SET                ((uint32_t volatile *)PINT3_MASK_SET) /* Pin Interrupt 3 Mask Set Register */
#define bfin_read_PINT3_MASK_SET()     bfin_read32(PINT3_MASK_SET)
#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
#define pPINT3_MASK_CLEAR              ((uint32_t volatile *)PINT3_MASK_CLEAR) /* Pin Interrupt 3 Mask Clear Register */
#define bfin_read_PINT3_MASK_CLEAR()   bfin_read32(PINT3_MASK_CLEAR)
#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
#define pPINT3_IRQ                     ((uint32_t volatile *)PINT3_IRQ) /* Pin Interrupt 3 Interrupt Request Register */
#define bfin_read_PINT3_IRQ()          bfin_read32(PINT3_IRQ)
#define bfin_write_PINT3_IRQ(val)      bfin_write32(PINT3_IRQ, val)
#define pPINT3_ASSIGN                  ((uint32_t volatile *)PINT3_ASSIGN) /* Pin Interrupt 3 Port Assign Register */
#define bfin_read_PINT3_ASSIGN()       bfin_read32(PINT3_ASSIGN)
#define bfin_write_PINT3_ASSIGN(val)   bfin_write32(PINT3_ASSIGN, val)
#define pPINT3_EDGE_SET                ((uint32_t volatile *)PINT3_EDGE_SET) /* Pin Interrupt 3 Edge-sensitivity Set Register */
#define bfin_read_PINT3_EDGE_SET()     bfin_read32(PINT3_EDGE_SET)
#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
#define pPINT3_EDGE_CLEAR              ((uint32_t volatile *)PINT3_EDGE_CLEAR) /* Pin Interrupt 3 Edge-sensitivity Clear Register */
#define bfin_read_PINT3_EDGE_CLEAR()   bfin_read32(PINT3_EDGE_CLEAR)
#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
#define pPINT3_INVERT_SET              ((uint32_t volatile *)PINT3_INVERT_SET) /* Pin Interrupt 3 Inversion Set Register */
#define bfin_read_PINT3_INVERT_SET()   bfin_read32(PINT3_INVERT_SET)
#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
#define pPINT3_INVERT_CLEAR            ((uint32_t volatile *)PINT3_INVERT_CLEAR) /* Pin Interrupt 3 Inversion Clear Register */
#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
#define pPINT3_PINSTATE                ((uint32_t volatile *)PINT3_PINSTATE) /* Pin Interrupt 3 Pin Status Register */
#define bfin_read_PINT3_PINSTATE()     bfin_read32(PINT3_PINSTATE)
#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
#define pPINT3_LATCH                   ((uint32_t volatile *)PINT3_LATCH) /* Pin Interrupt 3 Latch Register */
#define bfin_read_PINT3_LATCH()        bfin_read32(PINT3_LATCH)
#define bfin_write_PINT3_LATCH(val)    bfin_write32(PINT3_LATCH, val)
#define pTIMER0_CONFIG                 ((uint16_t volatile *)TIMER0_CONFIG) /* Timer 0 Configuration Register */
#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
#define pTIMER0_COUNTER                ((uint32_t volatile *)TIMER0_COUNTER) /* Timer 0 Counter Register */
#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
#define pTIMER0_PERIOD                 ((uint32_t volatile *)TIMER0_PERIOD) /* Timer 0 Period Register */
#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
#define pTIMER0_WIDTH                  ((uint32_t volatile *)TIMER0_WIDTH) /* Timer 0 Width Register */
#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
#define pTIMER1_CONFIG                 ((uint16_t volatile *)TIMER1_CONFIG) /* Timer 1 Configuration Register */
#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
#define pTIMER1_COUNTER                ((uint32_t volatile *)TIMER1_COUNTER) /* Timer 1 Counter Register */
#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
#define pTIMER1_PERIOD                 ((uint32_t volatile *)TIMER1_PERIOD) /* Timer 1 Period Register */
#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
#define pTIMER1_WIDTH                  ((uint32_t volatile *)TIMER1_WIDTH) /* Timer 1 Width Register */
#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
#define pTIMER2_CONFIG                 ((uint16_t volatile *)TIMER2_CONFIG) /* Timer 2 Configuration Register */
#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
#define pTIMER2_COUNTER                ((uint32_t volatile *)TIMER2_COUNTER) /* Timer 2 Counter Register */
#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
#define pTIMER2_PERIOD                 ((uint32_t volatile *)TIMER2_PERIOD) /* Timer 2 Period Register */
#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
#define pTIMER2_WIDTH                  ((uint32_t volatile *)TIMER2_WIDTH) /* Timer 2 Width Register */
#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
#define pTIMER3_CONFIG                 ((uint16_t volatile *)TIMER3_CONFIG) /* Timer 3 Configuration Register */
#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
#define pTIMER3_COUNTER                ((uint32_t volatile *)TIMER3_COUNTER) /* Timer 3 Counter Register */
#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
#define pTIMER3_PERIOD                 ((uint32_t volatile *)TIMER3_PERIOD) /* Timer 3 Period Register */
#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
#define pTIMER3_WIDTH                  ((uint32_t volatile *)TIMER3_WIDTH) /* Timer 3 Width Register */
#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
#define pTIMER4_CONFIG                 ((uint16_t volatile *)TIMER4_CONFIG) /* Timer 4 Configuration Register */
#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
#define pTIMER4_COUNTER                ((uint32_t volatile *)TIMER4_COUNTER) /* Timer 4 Counter Register */
#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
#define pTIMER4_PERIOD                 ((uint32_t volatile *)TIMER4_PERIOD) /* Timer 4 Period Register */
#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
#define pTIMER4_WIDTH                  ((uint32_t volatile *)TIMER4_WIDTH) /* Timer 4 Width Register */
#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
#define pTIMER5_CONFIG                 ((uint16_t volatile *)TIMER5_CONFIG) /* Timer 5 Configuration Register */
#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
#define pTIMER5_COUNTER                ((uint32_t volatile *)TIMER5_COUNTER) /* Timer 5 Counter Register */
#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
#define pTIMER5_PERIOD                 ((uint32_t volatile *)TIMER5_PERIOD) /* Timer 5 Period Register */
#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
#define pTIMER5_WIDTH                  ((uint32_t volatile *)TIMER5_WIDTH) /* Timer 5 Width Register */
#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
#define pTIMER6_CONFIG                 ((uint16_t volatile *)TIMER6_CONFIG) /* Timer 6 Configuration Register */
#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
#define pTIMER6_COUNTER                ((uint32_t volatile *)TIMER6_COUNTER) /* Timer 6 Counter Register */
#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
#define pTIMER6_PERIOD                 ((uint32_t volatile *)TIMER6_PERIOD) /* Timer 6 Period Register */
#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
#define pTIMER6_WIDTH                  ((uint32_t volatile *)TIMER6_WIDTH) /* Timer 6 Width Register */
#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
#define pTIMER7_CONFIG                 ((uint16_t volatile *)TIMER7_CONFIG) /* Timer 7 Configuration Register */
#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
#define pTIMER7_COUNTER                ((uint32_t volatile *)TIMER7_COUNTER) /* Timer 7 Counter Register */
#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
#define pTIMER7_PERIOD                 ((uint32_t volatile *)TIMER7_PERIOD) /* Timer 7 Period Register */
#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
#define pTIMER7_WIDTH                  ((uint32_t volatile *)TIMER7_WIDTH) /* Timer 7 Width Register */
#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
#define pTIMER8_CONFIG                 ((uint16_t volatile *)TIMER8_CONFIG) /* Timer 8 Configuration Register */
#define bfin_read_TIMER8_CONFIG()      bfin_read16(TIMER8_CONFIG)
#define bfin_write_TIMER8_CONFIG(val)  bfin_write16(TIMER8_CONFIG, val)
#define pTIMER8_COUNTER                ((uint32_t volatile *)TIMER8_COUNTER) /* Timer 8 Counter Register */
#define bfin_read_TIMER8_COUNTER()     bfin_read32(TIMER8_COUNTER)
#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
#define pTIMER8_PERIOD                 ((uint32_t volatile *)TIMER8_PERIOD) /* Timer 8 Period Register */
#define bfin_read_TIMER8_PERIOD()      bfin_read32(TIMER8_PERIOD)
#define bfin_write_TIMER8_PERIOD(val)  bfin_write32(TIMER8_PERIOD, val)
#define pTIMER8_WIDTH                  ((uint32_t volatile *)TIMER8_WIDTH) /* Timer 8 Width Register */
#define bfin_read_TIMER8_WIDTH()       bfin_read32(TIMER8_WIDTH)
#define bfin_write_TIMER8_WIDTH(val)   bfin_write32(TIMER8_WIDTH, val)
#define pTIMER9_CONFIG                 ((uint16_t volatile *)TIMER9_CONFIG) /* Timer 9 Configuration Register */
#define bfin_read_TIMER9_CONFIG()      bfin_read16(TIMER9_CONFIG)
#define bfin_write_TIMER9_CONFIG(val)  bfin_write16(TIMER9_CONFIG, val)
#define pTIMER9_COUNTER                ((uint32_t volatile *)TIMER9_COUNTER) /* Timer 9 Counter Register */
#define bfin_read_TIMER9_COUNTER()     bfin_read32(TIMER9_COUNTER)
#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
#define pTIMER9_PERIOD                 ((uint32_t volatile *)TIMER9_PERIOD) /* Timer 9 Period Register */
#define bfin_read_TIMER9_PERIOD()      bfin_read32(TIMER9_PERIOD)
#define bfin_write_TIMER9_PERIOD(val)  bfin_write32(TIMER9_PERIOD, val)
#define pTIMER9_WIDTH                  ((uint32_t volatile *)TIMER9_WIDTH) /* Timer 9 Width Register */
#define bfin_read_TIMER9_WIDTH()       bfin_read32(TIMER9_WIDTH)
#define bfin_write_TIMER9_WIDTH(val)   bfin_write32(TIMER9_WIDTH, val)
#define pTIMER10_CONFIG                ((uint16_t volatile *)TIMER10_CONFIG) /* Timer 10 Configuration Register */
#define bfin_read_TIMER10_CONFIG()     bfin_read16(TIMER10_CONFIG)
#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
#define pTIMER10_COUNTER               ((uint32_t volatile *)TIMER10_COUNTER) /* Timer 10 Counter Register */
#define bfin_read_TIMER10_COUNTER()    bfin_read32(TIMER10_COUNTER)
#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
#define pTIMER10_PERIOD                ((uint32_t volatile *)TIMER10_PERIOD) /* Timer 10 Period Register */
#define bfin_read_TIMER10_PERIOD()     bfin_read32(TIMER10_PERIOD)
#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
#define pTIMER10_WIDTH                 ((uint32_t volatile *)TIMER10_WIDTH) /* Timer 10 Width Register */
#define bfin_read_TIMER10_WIDTH()      bfin_read32(TIMER10_WIDTH)
#define bfin_write_TIMER10_WIDTH(val)  bfin_write32(TIMER10_WIDTH, val)
#define pTIMER_ENABLE0                 ((uint16_t volatile *)TIMER_ENABLE0) /* Timer Group of 8 Enable Register */
#define bfin_read_TIMER_ENABLE0()      bfin_read16(TIMER_ENABLE0)
#define bfin_write_TIMER_ENABLE0(val)  bfin_write16(TIMER_ENABLE0, val)
#define pTIMER_DISABLE0                ((uint16_t volatile *)TIMER_DISABLE0) /* Timer Group of 8 Disable Register */
#define bfin_read_TIMER_DISABLE0()     bfin_read16(TIMER_DISABLE0)
#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
#define pTIMER_STATUS0                 ((uint32_t volatile *)TIMER_STATUS0) /* Timer Group of 8 Status Register */
#define bfin_read_TIMER_STATUS0()      bfin_read32(TIMER_STATUS0)
#define bfin_write_TIMER_STATUS0(val)  bfin_write32(TIMER_STATUS0, val)
#define pTIMER_ENABLE1                 ((uint16_t volatile *)TIMER_ENABLE1) /* Timer Group of 3 Enable Register */
#define bfin_read_TIMER_ENABLE1()      bfin_read16(TIMER_ENABLE1)
#define bfin_write_TIMER_ENABLE1(val)  bfin_write16(TIMER_ENABLE1, val)
#define pTIMER_DISABLE1                ((uint16_t volatile *)TIMER_DISABLE1) /* Timer Group of 3 Disable Register */
#define bfin_read_TIMER_DISABLE1()     bfin_read16(TIMER_DISABLE1)
#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
#define pTIMER_STATUS1                 ((uint32_t volatile *)TIMER_STATUS1) /* Timer Group of 3 Status Register */
#define bfin_read_TIMER_STATUS1()      bfin_read32(TIMER_STATUS1)
#define bfin_write_TIMER_STATUS1(val)  bfin_write32(TIMER_STATUS1, val)
#define pTCNTL                         ((uint32_t volatile *)TCNTL) /* Core Timer Control Register */
#define bfin_read_TCNTL()              bfin_read32(TCNTL)
#define bfin_write_TCNTL(val)          bfin_write32(TCNTL, val)
#define pTCOUNT                        ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
#define bfin_read_TCOUNT()             bfin_read32(TCOUNT)
#define bfin_write_TCOUNT(val)         bfin_write32(TCOUNT, val)
#define pTPERIOD                       ((uint32_t volatile *)TPERIOD) /* Core Timer Period Register */
#define bfin_read_TPERIOD()            bfin_read32(TPERIOD)
#define bfin_write_TPERIOD(val)        bfin_write32(TPERIOD, val)
#define pTSCALE                        ((uint32_t volatile *)TSCALE) /* Core Timer Scale Register */
#define bfin_read_TSCALE()             bfin_read32(TSCALE)
#define bfin_write_TSCALE(val)         bfin_write32(TSCALE, val)
#define pWDOG_CTL                      ((uint16_t volatile *)WDOG_CTL) /* Watchdog Control Register */
#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
#define pWDOG_CNT                      ((uint32_t volatile *)WDOG_CNT) /* Watchdog Count Register */
#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
#define pWDOG_STAT                     ((uint32_t volatile *)WDOG_STAT) /* Watchdog Status Register */
#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
#define pCNT_CONFIG                    ((uint16_t volatile *)CNT_CONFIG) /* Configuration Register */
#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
#define pCNT_IMASK                     ((uint16_t volatile *)CNT_IMASK) /* Interrupt Mask Register */
#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
#define pCNT_STATUS                    ((uint16_t volatile *)CNT_STATUS) /* Status Register  */
#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
#define pCNT_COMMAND                   ((uint16_t volatile *)CNT_COMMAND) /* Command Register */
#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
#define pCNT_DEBOUNCE                  ((uint16_t volatile *)CNT_DEBOUNCE) /* Debounce Register */
#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
#define pCNT_COUNTER                   ((uint32_t volatile *)CNT_COUNTER) /* Counter Register */
#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
#define pCNT_MAX                       ((uint32_t volatile *)CNT_MAX) /* Maximal Count Register */
#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
#define pCNT_MIN                       ((uint32_t volatile *)CNT_MIN) /* Minimal Count Register */
#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
#define pRTC_STAT                      ((uint32_t volatile *)RTC_STAT) /* RTC Status Register */
#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
#define pRTC_ICTL                      ((uint16_t volatile *)RTC_ICTL) /* RTC Interrupt Control Register */
#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
#define pRTC_ISTAT                     ((uint16_t volatile *)RTC_ISTAT) /* RTC Interrupt Status Register */
#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
#define pRTC_SWCNT                     ((uint16_t volatile *)RTC_SWCNT) /* RTC Stopwatch Count Register */
#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
#define pRTC_ALARM                     ((uint32_t volatile *)RTC_ALARM) /* RTC Alarm Register */
#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
#define pRTC_PREN                      ((uint16_t volatile *)RTC_PREN) /* RTC Prescaler Enable Register */
#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
#define pOTP_CONTROL                   ((uint16_t volatile *)OTP_CONTROL) /* OTP/Fuse Control Register */
#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
#define pOTP_BEN                       ((uint16_t volatile *)OTP_BEN) /* OTP/Fuse Byte Enable */
#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
#define pOTP_STATUS                    ((uint16_t volatile *)OTP_STATUS) /* OTP/Fuse Status */
#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
#define pOTP_TIMING                    ((uint32_t volatile *)OTP_TIMING) /* OTP/Fuse Access Timing */
#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
#define pSECURE_SYSSWT                 ((uint32_t volatile *)SECURE_SYSSWT) /* Secure System Switches */
#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
#define pSECURE_CONTROL                ((uint16_t volatile *)SECURE_CONTROL) /* Secure Control */
#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
#define pSECURE_STATUS                 ((uint16_t volatile *)SECURE_STATUS) /* Secure Status */
#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
#define pOTP_DATA0                     ((uint32_t volatile *)OTP_DATA0) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
#define pOTP_DATA1                     ((uint32_t volatile *)OTP_DATA1) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
#define pOTP_DATA2                     ((uint32_t volatile *)OTP_DATA2) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
#define pOTP_DATA3                     ((uint32_t volatile *)OTP_DATA3) /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
#define pPLL_CTL                       ((uint16_t volatile *)PLL_CTL) /* PLL Control Register */
#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
#define pPLL_DIV                       ((uint16_t volatile *)PLL_DIV) /* PLL Divisor Register */
#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
#define pVR_CTL                        ((uint16_t volatile *)VR_CTL) /* Voltage Regulator Control Register */
#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
#define pPLL_STAT                      ((uint16_t volatile *)PLL_STAT) /* PLL Status Register */
#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
#define pPLL_LOCKCNT                   ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count Register */
#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
#define pNFC_CTL                       ((uint16_t volatile *)NFC_CTL) /* NAND Control Register */
#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
#define pNFC_STAT                      ((uint16_t volatile *)NFC_STAT) /* NAND Status Register */
#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
#define pNFC_IRQSTAT                   ((uint16_t volatile *)NFC_IRQSTAT) /* NAND Interrupt Status Register */
#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
#define pNFC_IRQMASK                   ((uint16_t volatile *)NFC_IRQMASK) /* NAND Interrupt Mask Register */
#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
#define pNFC_ECC0                      ((uint16_t volatile *)NFC_ECC0) /* NAND ECC Register 0 */
#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
#define pNFC_ECC1                      ((uint16_t volatile *)NFC_ECC1) /* NAND ECC Register 1 */
#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
#define pNFC_ECC2                      ((uint16_t volatile *)NFC_ECC2) /* NAND ECC Register 2 */
#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
#define pNFC_ECC3                      ((uint16_t volatile *)NFC_ECC3) /* NAND ECC Register 3 */
#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
#define pNFC_COUNT                     ((uint16_t volatile *)NFC_COUNT) /* NAND ECC Count Register */
#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
#define pNFC_RST                       ((uint16_t volatile *)NFC_RST) /* NAND ECC Reset Register */
#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
#define pNFC_PGCTL                     ((uint16_t volatile *)NFC_PGCTL) /* NAND Page Control Register */
#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
#define pNFC_READ                      ((uint16_t volatile *)NFC_READ) /* NAND Read Data Register */
#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
#define pNFC_ADDR                      ((uint16_t volatile *)NFC_ADDR) /* NAND Address Register */
#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
#define pNFC_CMD                       ((uint16_t volatile *)NFC_CMD) /* NAND Command Register */
#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
#define pNFC_DATA_WR                   ((uint16_t volatile *)NFC_DATA_WR) /* NAND Data Write Register */
#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
#define pNFC_DATA_RD                   ((uint16_t volatile *)NFC_DATA_RD) /* NAND Data Read Register */
#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
#define pEPPI0_STATUS                  ((uint16_t volatile *)EPPI0_STATUS) /* EPPI0 Status Register */
#define bfin_read_EPPI0_STATUS()       bfin_read16(EPPI0_STATUS)
#define bfin_write_EPPI0_STATUS(val)   bfin_write16(EPPI0_STATUS, val)
#define pEPPI0_HCOUNT                  ((uint16_t volatile *)EPPI0_HCOUNT) /* EPPI0 Horizontal Transfer Count Register */
#define bfin_read_EPPI0_HCOUNT()       bfin_read16(EPPI0_HCOUNT)
#define bfin_write_EPPI0_HCOUNT(val)   bfin_write16(EPPI0_HCOUNT, val)
#define pEPPI0_HDELAY                  ((uint16_t volatile *)EPPI0_HDELAY) /* EPPI0 Horizontal Delay Count Register */
#define bfin_read_EPPI0_HDELAY()       bfin_read16(EPPI0_HDELAY)
#define bfin_write_EPPI0_HDELAY(val)   bfin_write16(EPPI0_HDELAY, val)
#define pEPPI0_VCOUNT                  ((uint16_t volatile *)EPPI0_VCOUNT) /* EPPI0 Vertical Transfer Count Register */
#define bfin_read_EPPI0_VCOUNT()       bfin_read16(EPPI0_VCOUNT)
#define bfin_write_EPPI0_VCOUNT(val)   bfin_write16(EPPI0_VCOUNT, val)
#define pEPPI0_VDELAY                  ((uint16_t volatile *)EPPI0_VDELAY) /* EPPI0 Vertical Delay Count Register */
#define bfin_read_EPPI0_VDELAY()       bfin_read16(EPPI0_VDELAY)
#define bfin_write_EPPI0_VDELAY(val)   bfin_write16(EPPI0_VDELAY, val)
#define pEPPI0_FRAME                   ((uint16_t volatile *)EPPI0_FRAME) /* EPPI0 Lines per Frame Register */
#define bfin_read_EPPI0_FRAME()        bfin_read16(EPPI0_FRAME)
#define bfin_write_EPPI0_FRAME(val)    bfin_write16(EPPI0_FRAME, val)
#define pEPPI0_LINE                    ((uint16_t volatile *)EPPI0_LINE) /* EPPI0 Samples per Line Register */
#define bfin_read_EPPI0_LINE()         bfin_read16(EPPI0_LINE)
#define bfin_write_EPPI0_LINE(val)     bfin_write16(EPPI0_LINE, val)
#define pEPPI0_CLKDIV                  ((uint16_t volatile *)EPPI0_CLKDIV) /* EPPI0 Clock Divide Register */
#define bfin_read_EPPI0_CLKDIV()       bfin_read16(EPPI0_CLKDIV)
#define bfin_write_EPPI0_CLKDIV(val)   bfin_write16(EPPI0_CLKDIV, val)
#define pEPPI0_CONTROL                 ((uint32_t volatile *)EPPI0_CONTROL) /* EPPI0 Control Register */
#define bfin_read_EPPI0_CONTROL()      bfin_read32(EPPI0_CONTROL)
#define bfin_write_EPPI0_CONTROL(val)  bfin_write32(EPPI0_CONTROL, val)
#define pEPPI0_FS1W_HBL                ((uint32_t volatile *)EPPI0_FS1W_HBL) /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI0_FS1W_HBL()     bfin_read32(EPPI0_FS1W_HBL)
#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
#define pEPPI0_FS1P_AVPL               ((uint32_t volatile *)EPPI0_FS1P_AVPL) /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
#define bfin_read_EPPI0_FS1P_AVPL()    bfin_read32(EPPI0_FS1P_AVPL)
#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
#define pEPPI0_FS2W_LVB                ((uint32_t volatile *)EPPI0_FS2W_LVB) /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
#define bfin_read_EPPI0_FS2W_LVB()     bfin_read32(EPPI0_FS2W_LVB)
#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
#define pEPPI0_FS2P_LAVF               ((uint32_t volatile *)EPPI0_FS2P_LAVF) /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
#define bfin_read_EPPI0_FS2P_LAVF()    bfin_read32(EPPI0_FS2P_LAVF)
#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
#define pEPPI0_CLIP                    ((uint32_t volatile *)EPPI0_CLIP) /* EPPI0 Clipping Register */
#define bfin_read_EPPI0_CLIP()         bfin_read32(EPPI0_CLIP)
#define bfin_write_EPPI0_CLIP(val)     bfin_write32(EPPI0_CLIP, val)
#define pEPPI1_STATUS                  ((uint16_t volatile *)EPPI1_STATUS) /* EPPI1 Status Register */
#define bfin_read_EPPI1_STATUS()       bfin_read16(EPPI1_STATUS)
#define bfin_write_EPPI1_STATUS(val)   bfin_write16(EPPI1_STATUS, val)
#define pEPPI1_HCOUNT                  ((uint16_t volatile *)EPPI1_HCOUNT) /* EPPI1 Horizontal Transfer Count Register */
#define bfin_read_EPPI1_HCOUNT()       bfin_read16(EPPI1_HCOUNT)
#define bfin_write_EPPI1_HCOUNT(val)   bfin_write16(EPPI1_HCOUNT, val)
#define pEPPI1_HDELAY                  ((uint16_t volatile *)EPPI1_HDELAY) /* EPPI1 Horizontal Delay Count Register */
#define bfin_read_EPPI1_HDELAY()       bfin_read16(EPPI1_HDELAY)
#define bfin_write_EPPI1_HDELAY(val)   bfin_write16(EPPI1_HDELAY, val)
#define pEPPI1_VCOUNT                  ((uint16_t volatile *)EPPI1_VCOUNT) /* EPPI1 Vertical Transfer Count Register */
#define bfin_read_EPPI1_VCOUNT()       bfin_read16(EPPI1_VCOUNT)
#define bfin_write_EPPI1_VCOUNT(val)   bfin_write16(EPPI1_VCOUNT, val)
#define pEPPI1_VDELAY                  ((uint16_t volatile *)EPPI1_VDELAY) /* EPPI1 Vertical Delay Count Register */
#define bfin_read_EPPI1_VDELAY()       bfin_read16(EPPI1_VDELAY)
#define bfin_write_EPPI1_VDELAY(val)   bfin_write16(EPPI1_VDELAY, val)
#define pEPPI1_FRAME                   ((uint16_t volatile *)EPPI1_FRAME) /* EPPI1 Lines per Frame Register */
#define bfin_read_EPPI1_FRAME()        bfin_read16(EPPI1_FRAME)
#define bfin_write_EPPI1_FRAME(val)    bfin_write16(EPPI1_FRAME, val)
#define pEPPI1_LINE                    ((uint16_t volatile *)EPPI1_LINE) /* EPPI1 Samples per Line Register */
#define bfin_read_EPPI1_LINE()         bfin_read16(EPPI1_LINE)
#define bfin_write_EPPI1_LINE(val)     bfin_write16(EPPI1_LINE, val)
#define pEPPI1_CLKDIV                  ((uint16_t volatile *)EPPI1_CLKDIV) /* EPPI1 Clock Divide Register */
#define bfin_read_EPPI1_CLKDIV()       bfin_read16(EPPI1_CLKDIV)
#define bfin_write_EPPI1_CLKDIV(val)   bfin_write16(EPPI1_CLKDIV, val)
#define pEPPI1_CONTROL                 ((uint32_t volatile *)EPPI1_CONTROL) /* EPPI1 Control Register */
#define bfin_read_EPPI1_CONTROL()      bfin_read32(EPPI1_CONTROL)
#define bfin_write_EPPI1_CONTROL(val)  bfin_write32(EPPI1_CONTROL, val)
#define pEPPI1_FS1W_HBL                ((uint32_t volatile *)EPPI1_FS1W_HBL) /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI1_FS1W_HBL()     bfin_read32(EPPI1_FS1W_HBL)
#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
#define pEPPI1_FS1P_AVPL               ((uint32_t volatile *)EPPI1_FS1P_AVPL) /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
#define bfin_read_EPPI1_FS1P_AVPL()    bfin_read32(EPPI1_FS1P_AVPL)
#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
#define pEPPI1_FS2W_LVB                ((uint32_t volatile *)EPPI1_FS2W_LVB) /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
#define bfin_read_EPPI1_FS2W_LVB()     bfin_read32(EPPI1_FS2W_LVB)
#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
#define pEPPI1_FS2P_LAVF               ((uint32_t volatile *)EPPI1_FS2P_LAVF) /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
#define bfin_read_EPPI1_FS2P_LAVF()    bfin_read32(EPPI1_FS2P_LAVF)
#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
#define pEPPI1_CLIP                    ((uint32_t volatile *)EPPI1_CLIP) /* EPPI1 Clipping Register */
#define bfin_read_EPPI1_CLIP()         bfin_read32(EPPI1_CLIP)
#define bfin_write_EPPI1_CLIP(val)     bfin_write32(EPPI1_CLIP, val)
#define pEPPI2_STATUS                  ((uint16_t volatile *)EPPI2_STATUS) /* EPPI2 Status Register */
#define bfin_read_EPPI2_STATUS()       bfin_read16(EPPI2_STATUS)
#define bfin_write_EPPI2_STATUS(val)   bfin_write16(EPPI2_STATUS, val)
#define pEPPI2_HCOUNT                  ((uint16_t volatile *)EPPI2_HCOUNT) /* EPPI2 Horizontal Transfer Count Register */
#define bfin_read_EPPI2_HCOUNT()       bfin_read16(EPPI2_HCOUNT)
#define bfin_write_EPPI2_HCOUNT(val)   bfin_write16(EPPI2_HCOUNT, val)
#define pEPPI2_HDELAY                  ((uint16_t volatile *)EPPI2_HDELAY) /* EPPI2 Horizontal Delay Count Register */
#define bfin_read_EPPI2_HDELAY()       bfin_read16(EPPI2_HDELAY)
#define bfin_write_EPPI2_HDELAY(val)   bfin_write16(EPPI2_HDELAY, val)
#define pEPPI2_VCOUNT                  ((uint16_t volatile *)EPPI2_VCOUNT) /* EPPI2 Vertical Transfer Count Register */
#define bfin_read_EPPI2_VCOUNT()       bfin_read16(EPPI2_VCOUNT)
#define bfin_write_EPPI2_VCOUNT(val)   bfin_write16(EPPI2_VCOUNT, val)
#define pEPPI2_VDELAY                  ((uint16_t volatile *)EPPI2_VDELAY) /* EPPI2 Vertical Delay Count Register */
#define bfin_read_EPPI2_VDELAY()       bfin_read16(EPPI2_VDELAY)
#define bfin_write_EPPI2_VDELAY(val)   bfin_write16(EPPI2_VDELAY, val)
#define pEPPI2_FRAME                   ((uint16_t volatile *)EPPI2_FRAME) /* EPPI2 Lines per Frame Register */
#define bfin_read_EPPI2_FRAME()        bfin_read16(EPPI2_FRAME)
#define bfin_write_EPPI2_FRAME(val)    bfin_write16(EPPI2_FRAME, val)
#define pEPPI2_LINE                    ((uint16_t volatile *)EPPI2_LINE) /* EPPI2 Samples per Line Register */
#define bfin_read_EPPI2_LINE()         bfin_read16(EPPI2_LINE)
#define bfin_write_EPPI2_LINE(val)     bfin_write16(EPPI2_LINE, val)
#define pEPPI2_CLKDIV                  ((uint16_t volatile *)EPPI2_CLKDIV) /* EPPI2 Clock Divide Register */
#define bfin_read_EPPI2_CLKDIV()       bfin_read16(EPPI2_CLKDIV)
#define bfin_write_EPPI2_CLKDIV(val)   bfin_write16(EPPI2_CLKDIV, val)
#define pEPPI2_CONTROL                 ((uint32_t volatile *)EPPI2_CONTROL) /* EPPI2 Control Register */
#define bfin_read_EPPI2_CONTROL()      bfin_read32(EPPI2_CONTROL)
#define bfin_write_EPPI2_CONTROL(val)  bfin_write32(EPPI2_CONTROL, val)
#define pEPPI2_FS1W_HBL                ((uint32_t volatile *)EPPI2_FS1W_HBL) /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
#define bfin_read_EPPI2_FS1W_HBL()     bfin_read32(EPPI2_FS1W_HBL)
#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
#define pEPPI2_FS1P_AVPL               ((uint32_t volatile *)EPPI2_FS1P_AVPL) /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
#define bfin_read_EPPI2_FS1P_AVPL()    bfin_read32(EPPI2_FS1P_AVPL)
#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
#define pEPPI2_FS2W_LVB                ((uint32_t volatile *)EPPI2_FS2W_LVB) /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
#define bfin_read_EPPI2_FS2W_LVB()     bfin_read32(EPPI2_FS2W_LVB)
#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
#define pEPPI2_FS2P_LAVF               ((uint32_t volatile *)EPPI2_FS2P_LAVF) /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
#define bfin_read_EPPI2_FS2P_LAVF()    bfin_read32(EPPI2_FS2P_LAVF)
#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
#define pEPPI2_CLIP                    ((uint32_t volatile *)EPPI2_CLIP) /* EPPI2 Clipping Register */
#define bfin_read_EPPI2_CLIP()         bfin_read32(EPPI2_CLIP)
#define bfin_write_EPPI2_CLIP(val)     bfin_write32(EPPI2_CLIP, val)
#define pCAN0_MC1                      ((uint16_t volatile *)CAN0_MC1) /* CAN Controller 0 Mailbox Configuration Register 1 */
#define bfin_read_CAN0_MC1()           bfin_read16(CAN0_MC1)
#define bfin_write_CAN0_MC1(val)       bfin_write16(CAN0_MC1, val)
#define pCAN0_MD1                      ((uint16_t volatile *)CAN0_MD1) /* CAN Controller 0 Mailbox Direction Register 1 */
#define bfin_read_CAN0_MD1()           bfin_read16(CAN0_MD1)
#define bfin_write_CAN0_MD1(val)       bfin_write16(CAN0_MD1, val)
#define pCAN0_TRS1                     ((uint16_t volatile *)CAN0_TRS1) /* CAN Controller 0 Transmit Request Set Register 1 */
#define bfin_read_CAN0_TRS1()          bfin_read16(CAN0_TRS1)
#define bfin_write_CAN0_TRS1(val)      bfin_write16(CAN0_TRS1, val)
#define pCAN0_TRR1                     ((uint16_t volatile *)CAN0_TRR1) /* CAN Controller 0 Transmit Request Reset Register 1 */
#define bfin_read_CAN0_TRR1()          bfin_read16(CAN0_TRR1)
#define bfin_write_CAN0_TRR1(val)      bfin_write16(CAN0_TRR1, val)
#define pCAN0_TA1                      ((uint16_t volatile *)CAN0_TA1) /* CAN Controller 0 Transmit Acknowledge Register 1 */
#define bfin_read_CAN0_TA1()           bfin_read16(CAN0_TA1)
#define bfin_write_CAN0_TA1(val)       bfin_write16(CAN0_TA1, val)
#define pCAN0_AA1                      ((uint16_t volatile *)CAN0_AA1) /* CAN Controller 0 Abort Acknowledge Register 1 */
#define bfin_read_CAN0_AA1()           bfin_read16(CAN0_AA1)
#define bfin_write_CAN0_AA1(val)       bfin_write16(CAN0_AA1, val)
#define pCAN0_RMP1                     ((uint16_t volatile *)CAN0_RMP1) /* CAN Controller 0 Receive Message Pending Register 1 */
#define bfin_read_CAN0_RMP1()          bfin_read16(CAN0_RMP1)
#define bfin_write_CAN0_RMP1(val)      bfin_write16(CAN0_RMP1, val)
#define pCAN0_RML1                     ((uint16_t volatile *)CAN0_RML1) /* CAN Controller 0 Receive Message Lost Register 1 */
#define bfin_read_CAN0_RML1()          bfin_read16(CAN0_RML1)
#define bfin_write_CAN0_RML1(val)      bfin_write16(CAN0_RML1, val)
#define pCAN0_MBTIF1                   ((uint16_t volatile *)CAN0_MBTIF1) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBTIF1()        bfin_read16(CAN0_MBTIF1)
#define bfin_write_CAN0_MBTIF1(val)    bfin_write16(CAN0_MBTIF1, val)
#define pCAN0_MBRIF1                   ((uint16_t volatile *)CAN0_MBRIF1) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN0_MBRIF1()        bfin_read16(CAN0_MBRIF1)
#define bfin_write_CAN0_MBRIF1(val)    bfin_write16(CAN0_MBRIF1, val)
#define pCAN0_MBIM1                    ((uint16_t volatile *)CAN0_MBIM1) /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN0_MBIM1()         bfin_read16(CAN0_MBIM1)
#define bfin_write_CAN0_MBIM1(val)     bfin_write16(CAN0_MBIM1, val)
#define pCAN0_RFH1                     ((uint16_t volatile *)CAN0_RFH1) /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN0_RFH1()          bfin_read16(CAN0_RFH1)
#define bfin_write_CAN0_RFH1(val)      bfin_write16(CAN0_RFH1, val)
#define pCAN0_OPSS1                    ((uint16_t volatile *)CAN0_OPSS1) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN0_OPSS1()         bfin_read16(CAN0_OPSS1)
#define bfin_write_CAN0_OPSS1(val)     bfin_write16(CAN0_OPSS1, val)
#define pCAN0_MC2                      ((uint16_t volatile *)CAN0_MC2) /* CAN Controller 0 Mailbox Configuration Register 2 */
#define bfin_read_CAN0_MC2()           bfin_read16(CAN0_MC2)
#define bfin_write_CAN0_MC2(val)       bfin_write16(CAN0_MC2, val)
#define pCAN0_MD2                      ((uint16_t volatile *)CAN0_MD2) /* CAN Controller 0 Mailbox Direction Register 2 */
#define bfin_read_CAN0_MD2()           bfin_read16(CAN0_MD2)
#define bfin_write_CAN0_MD2(val)       bfin_write16(CAN0_MD2, val)
#define pCAN0_TRS2                     ((uint16_t volatile *)CAN0_TRS2) /* CAN Controller 0 Transmit Request Set Register 2 */
#define bfin_read_CAN0_TRS2()          bfin_read16(CAN0_TRS2)
#define bfin_write_CAN0_TRS2(val)      bfin_write16(CAN0_TRS2, val)
#define pCAN0_TRR2                     ((uint16_t volatile *)CAN0_TRR2) /* CAN Controller 0 Transmit Request Reset Register 2 */
#define bfin_read_CAN0_TRR2()          bfin_read16(CAN0_TRR2)
#define bfin_write_CAN0_TRR2(val)      bfin_write16(CAN0_TRR2, val)
#define pCAN0_TA2                      ((uint16_t volatile *)CAN0_TA2) /* CAN Controller 0 Transmit Acknowledge Register 2 */
#define bfin_read_CAN0_TA2()           bfin_read16(CAN0_TA2)
#define bfin_write_CAN0_TA2(val)       bfin_write16(CAN0_TA2, val)
#define pCAN0_AA2                      ((uint16_t volatile *)CAN0_AA2) /* CAN Controller 0 Abort Acknowledge Register 2 */
#define bfin_read_CAN0_AA2()           bfin_read16(CAN0_AA2)
#define bfin_write_CAN0_AA2(val)       bfin_write16(CAN0_AA2, val)
#define pCAN0_RMP2                     ((uint16_t volatile *)CAN0_RMP2) /* CAN Controller 0 Receive Message Pending Register 2 */
#define bfin_read_CAN0_RMP2()          bfin_read16(CAN0_RMP2)
#define bfin_write_CAN0_RMP2(val)      bfin_write16(CAN0_RMP2, val)
#define pCAN0_RML2                     ((uint16_t volatile *)CAN0_RML2) /* CAN Controller 0 Receive Message Lost Register 2 */
#define bfin_read_CAN0_RML2()          bfin_read16(CAN0_RML2)
#define bfin_write_CAN0_RML2(val)      bfin_write16(CAN0_RML2, val)
#define pCAN0_MBTIF2                   ((uint16_t volatile *)CAN0_MBTIF2) /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBTIF2()        bfin_read16(CAN0_MBTIF2)
#define bfin_write_CAN0_MBTIF2(val)    bfin_write16(CAN0_MBTIF2, val)
#define pCAN0_MBRIF2                   ((uint16_t volatile *)CAN0_MBRIF2) /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN0_MBRIF2()        bfin_read16(CAN0_MBRIF2)
#define bfin_write_CAN0_MBRIF2(val)    bfin_write16(CAN0_MBRIF2, val)
#define pCAN0_MBIM2                    ((uint16_t volatile *)CAN0_MBIM2) /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN0_MBIM2()         bfin_read16(CAN0_MBIM2)
#define bfin_write_CAN0_MBIM2(val)     bfin_write16(CAN0_MBIM2, val)
#define pCAN0_RFH2                     ((uint16_t volatile *)CAN0_RFH2) /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN0_RFH2()          bfin_read16(CAN0_RFH2)
#define bfin_write_CAN0_RFH2(val)      bfin_write16(CAN0_RFH2, val)
#define pCAN0_OPSS2                    ((uint16_t volatile *)CAN0_OPSS2) /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN0_OPSS2()         bfin_read16(CAN0_OPSS2)
#define bfin_write_CAN0_OPSS2(val)     bfin_write16(CAN0_OPSS2, val)
#define pCAN0_CLOCK                    ((uint16_t volatile *)CAN0_CLOCK) /* CAN Controller 0 Clock Register */
#define bfin_read_CAN0_CLOCK()         bfin_read16(CAN0_CLOCK)
#define bfin_write_CAN0_CLOCK(val)     bfin_write16(CAN0_CLOCK, val)
#define pCAN0_TIMING                   ((uint16_t volatile *)CAN0_TIMING) /* CAN Controller 0 Timing Register */
#define bfin_read_CAN0_TIMING()        bfin_read16(CAN0_TIMING)
#define bfin_write_CAN0_TIMING(val)    bfin_write16(CAN0_TIMING, val)
#define pCAN0_DEBUG                    ((uint16_t volatile *)CAN0_DEBUG) /* CAN Controller 0 Debug Register */
#define bfin_read_CAN0_DEBUG()         bfin_read16(CAN0_DEBUG)
#define bfin_write_CAN0_DEBUG(val)     bfin_write16(CAN0_DEBUG, val)
#define pCAN0_STATUS                   ((uint16_t volatile *)CAN0_STATUS) /* CAN Controller 0 Global Status Register */
#define bfin_read_CAN0_STATUS()        bfin_read16(CAN0_STATUS)
#define bfin_write_CAN0_STATUS(val)    bfin_write16(CAN0_STATUS, val)
#define pCAN0_CEC                      ((uint16_t volatile *)CAN0_CEC) /* CAN Controller 0 Error Counter Register */
#define bfin_read_CAN0_CEC()           bfin_read16(CAN0_CEC)
#define bfin_write_CAN0_CEC(val)       bfin_write16(CAN0_CEC, val)
#define pCAN0_GIS                      ((uint16_t volatile *)CAN0_GIS) /* CAN Controller 0 Global Interrupt Status Register */
#define bfin_read_CAN0_GIS()           bfin_read16(CAN0_GIS)
#define bfin_write_CAN0_GIS(val)       bfin_write16(CAN0_GIS, val)
#define pCAN0_GIM                      ((uint16_t volatile *)CAN0_GIM) /* CAN Controller 0 Global Interrupt Mask Register */
#define bfin_read_CAN0_GIM()           bfin_read16(CAN0_GIM)
#define bfin_write_CAN0_GIM(val)       bfin_write16(CAN0_GIM, val)
#define pCAN0_GIF                      ((uint16_t volatile *)CAN0_GIF) /* CAN Controller 0 Global Interrupt Flag Register */
#define bfin_read_CAN0_GIF()           bfin_read16(CAN0_GIF)
#define bfin_write_CAN0_GIF(val)       bfin_write16(CAN0_GIF, val)
#define pCAN0_CONTROL                  ((uint16_t volatile *)CAN0_CONTROL) /* CAN Controller 0 Master Control Register */
#define bfin_read_CAN0_CONTROL()       bfin_read16(CAN0_CONTROL)
#define bfin_write_CAN0_CONTROL(val)   bfin_write16(CAN0_CONTROL, val)
#define pCAN0_INTR                     ((uint16_t volatile *)CAN0_INTR) /* CAN Controller 0 Interrupt Pending Register */
#define bfin_read_CAN0_INTR()          bfin_read16(CAN0_INTR)
#define bfin_write_CAN0_INTR(val)      bfin_write16(CAN0_INTR, val)
#define pCAN0_MBTD                     ((uint16_t volatile *)CAN0_MBTD) /* CAN Controller 0 Mailbox Temporary Disable Register */
#define bfin_read_CAN0_MBTD()          bfin_read16(CAN0_MBTD)
#define bfin_write_CAN0_MBTD(val)      bfin_write16(CAN0_MBTD, val)
#define pCAN0_EWR                      ((uint16_t volatile *)CAN0_EWR) /* CAN Controller 0 Programmable Warning Level Register */
#define bfin_read_CAN0_EWR()           bfin_read16(CAN0_EWR)
#define bfin_write_CAN0_EWR(val)       bfin_write16(CAN0_EWR, val)
#define pCAN0_ESR                      ((uint16_t volatile *)CAN0_ESR) /* CAN Controller 0 Error Status Register */
#define bfin_read_CAN0_ESR()           bfin_read16(CAN0_ESR)
#define bfin_write_CAN0_ESR(val)       bfin_write16(CAN0_ESR, val)
#define pCAN0_UCCNT                    ((uint16_t volatile *)CAN0_UCCNT) /* CAN Controller 0 Universal Counter Register */
#define bfin_read_CAN0_UCCNT()         bfin_read16(CAN0_UCCNT)
#define bfin_write_CAN0_UCCNT(val)     bfin_write16(CAN0_UCCNT, val)
#define pCAN0_UCRC                     ((uint16_t volatile *)CAN0_UCRC) /* CAN Controller 0 Universal Counter Force Reload Register */
#define bfin_read_CAN0_UCRC()          bfin_read16(CAN0_UCRC)
#define bfin_write_CAN0_UCRC(val)      bfin_write16(CAN0_UCRC, val)
#define pCAN0_UCCNF                    ((uint16_t volatile *)CAN0_UCCNF) /* CAN Controller 0 Universal Counter Configuration Register */
#define bfin_read_CAN0_UCCNF()         bfin_read16(CAN0_UCCNF)
#define bfin_write_CAN0_UCCNF(val)     bfin_write16(CAN0_UCCNF, val)
#define pCAN0_AM00L                    ((uint16_t volatile *)CAN0_AM00L) /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN0_AM00L()         bfin_read16(CAN0_AM00L)
#define bfin_write_CAN0_AM00L(val)     bfin_write16(CAN0_AM00L, val)
#define pCAN0_AM00H                    ((uint16_t volatile *)CAN0_AM00H) /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM00H()         bfin_read16(CAN0_AM00H)
#define bfin_write_CAN0_AM00H(val)     bfin_write16(CAN0_AM00H, val)
#define pCAN0_AM01L                    ((uint16_t volatile *)CAN0_AM01L) /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN0_AM01L()         bfin_read16(CAN0_AM01L)
#define bfin_write_CAN0_AM01L(val)     bfin_write16(CAN0_AM01L, val)
#define pCAN0_AM01H                    ((uint16_t volatile *)CAN0_AM01H) /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM01H()         bfin_read16(CAN0_AM01H)
#define bfin_write_CAN0_AM01H(val)     bfin_write16(CAN0_AM01H, val)
#define pCAN0_AM02L                    ((uint16_t volatile *)CAN0_AM02L) /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN0_AM02L()         bfin_read16(CAN0_AM02L)
#define bfin_write_CAN0_AM02L(val)     bfin_write16(CAN0_AM02L, val)
#define pCAN0_AM02H                    ((uint16_t volatile *)CAN0_AM02H) /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM02H()         bfin_read16(CAN0_AM02H)
#define bfin_write_CAN0_AM02H(val)     bfin_write16(CAN0_AM02H, val)
#define pCAN0_AM03L                    ((uint16_t volatile *)CAN0_AM03L) /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN0_AM03L()         bfin_read16(CAN0_AM03L)
#define bfin_write_CAN0_AM03L(val)     bfin_write16(CAN0_AM03L, val)
#define pCAN0_AM03H                    ((uint16_t volatile *)CAN0_AM03H) /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM03H()         bfin_read16(CAN0_AM03H)
#define bfin_write_CAN0_AM03H(val)     bfin_write16(CAN0_AM03H, val)
#define pCAN0_AM04L                    ((uint16_t volatile *)CAN0_AM04L) /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN0_AM04L()         bfin_read16(CAN0_AM04L)
#define bfin_write_CAN0_AM04L(val)     bfin_write16(CAN0_AM04L, val)
#define pCAN0_AM04H                    ((uint16_t volatile *)CAN0_AM04H) /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM04H()         bfin_read16(CAN0_AM04H)
#define bfin_write_CAN0_AM04H(val)     bfin_write16(CAN0_AM04H, val)
#define pCAN0_AM05L                    ((uint16_t volatile *)CAN0_AM05L) /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN0_AM05L()         bfin_read16(CAN0_AM05L)
#define bfin_write_CAN0_AM05L(val)     bfin_write16(CAN0_AM05L, val)
#define pCAN0_AM05H                    ((uint16_t volatile *)CAN0_AM05H) /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM05H()         bfin_read16(CAN0_AM05H)
#define bfin_write_CAN0_AM05H(val)     bfin_write16(CAN0_AM05H, val)
#define pCAN0_AM06L                    ((uint16_t volatile *)CAN0_AM06L) /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN0_AM06L()         bfin_read16(CAN0_AM06L)
#define bfin_write_CAN0_AM06L(val)     bfin_write16(CAN0_AM06L, val)
#define pCAN0_AM06H                    ((uint16_t volatile *)CAN0_AM06H) /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM06H()         bfin_read16(CAN0_AM06H)
#define bfin_write_CAN0_AM06H(val)     bfin_write16(CAN0_AM06H, val)
#define pCAN0_AM07L                    ((uint16_t volatile *)CAN0_AM07L) /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN0_AM07L()         bfin_read16(CAN0_AM07L)
#define bfin_write_CAN0_AM07L(val)     bfin_write16(CAN0_AM07L, val)
#define pCAN0_AM07H                    ((uint16_t volatile *)CAN0_AM07H) /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM07H()         bfin_read16(CAN0_AM07H)
#define bfin_write_CAN0_AM07H(val)     bfin_write16(CAN0_AM07H, val)
#define pCAN0_AM08L                    ((uint16_t volatile *)CAN0_AM08L) /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN0_AM08L()         bfin_read16(CAN0_AM08L)
#define bfin_write_CAN0_AM08L(val)     bfin_write16(CAN0_AM08L, val)
#define pCAN0_AM08H                    ((uint16_t volatile *)CAN0_AM08H) /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM08H()         bfin_read16(CAN0_AM08H)
#define bfin_write_CAN0_AM08H(val)     bfin_write16(CAN0_AM08H, val)
#define pCAN0_AM09L                    ((uint16_t volatile *)CAN0_AM09L) /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN0_AM09L()         bfin_read16(CAN0_AM09L)
#define bfin_write_CAN0_AM09L(val)     bfin_write16(CAN0_AM09L, val)
#define pCAN0_AM09H                    ((uint16_t volatile *)CAN0_AM09H) /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM09H()         bfin_read16(CAN0_AM09H)
#define bfin_write_CAN0_AM09H(val)     bfin_write16(CAN0_AM09H, val)
#define pCAN0_AM10L                    ((uint16_t volatile *)CAN0_AM10L) /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN0_AM10L()         bfin_read16(CAN0_AM10L)
#define bfin_write_CAN0_AM10L(val)     bfin_write16(CAN0_AM10L, val)
#define pCAN0_AM10H                    ((uint16_t volatile *)CAN0_AM10H) /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM10H()         bfin_read16(CAN0_AM10H)
#define bfin_write_CAN0_AM10H(val)     bfin_write16(CAN0_AM10H, val)
#define pCAN0_AM11L                    ((uint16_t volatile *)CAN0_AM11L) /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN0_AM11L()         bfin_read16(CAN0_AM11L)
#define bfin_write_CAN0_AM11L(val)     bfin_write16(CAN0_AM11L, val)
#define pCAN0_AM11H                    ((uint16_t volatile *)CAN0_AM11H) /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM11H()         bfin_read16(CAN0_AM11H)
#define bfin_write_CAN0_AM11H(val)     bfin_write16(CAN0_AM11H, val)
#define pCAN0_AM12L                    ((uint16_t volatile *)CAN0_AM12L) /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN0_AM12L()         bfin_read16(CAN0_AM12L)
#define bfin_write_CAN0_AM12L(val)     bfin_write16(CAN0_AM12L, val)
#define pCAN0_AM12H                    ((uint16_t volatile *)CAN0_AM12H) /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM12H()         bfin_read16(CAN0_AM12H)
#define bfin_write_CAN0_AM12H(val)     bfin_write16(CAN0_AM12H, val)
#define pCAN0_AM13L                    ((uint16_t volatile *)CAN0_AM13L) /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN0_AM13L()         bfin_read16(CAN0_AM13L)
#define bfin_write_CAN0_AM13L(val)     bfin_write16(CAN0_AM13L, val)
#define pCAN0_AM13H                    ((uint16_t volatile *)CAN0_AM13H) /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM13H()         bfin_read16(CAN0_AM13H)
#define bfin_write_CAN0_AM13H(val)     bfin_write16(CAN0_AM13H, val)
#define pCAN0_AM14L                    ((uint16_t volatile *)CAN0_AM14L) /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN0_AM14L()         bfin_read16(CAN0_AM14L)
#define bfin_write_CAN0_AM14L(val)     bfin_write16(CAN0_AM14L, val)
#define pCAN0_AM14H                    ((uint16_t volatile *)CAN0_AM14H) /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM14H()         bfin_read16(CAN0_AM14H)
#define bfin_write_CAN0_AM14H(val)     bfin_write16(CAN0_AM14H, val)
#define pCAN0_AM15L                    ((uint16_t volatile *)CAN0_AM15L) /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN0_AM15L()         bfin_read16(CAN0_AM15L)
#define bfin_write_CAN0_AM15L(val)     bfin_write16(CAN0_AM15L, val)
#define pCAN0_AM15H                    ((uint16_t volatile *)CAN0_AM15H) /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM15H()         bfin_read16(CAN0_AM15H)
#define bfin_write_CAN0_AM15H(val)     bfin_write16(CAN0_AM15H, val)
#define pCAN0_AM16L                    ((uint16_t volatile *)CAN0_AM16L) /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN0_AM16L()         bfin_read16(CAN0_AM16L)
#define bfin_write_CAN0_AM16L(val)     bfin_write16(CAN0_AM16L, val)
#define pCAN0_AM16H                    ((uint16_t volatile *)CAN0_AM16H) /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM16H()         bfin_read16(CAN0_AM16H)
#define bfin_write_CAN0_AM16H(val)     bfin_write16(CAN0_AM16H, val)
#define pCAN0_AM17L                    ((uint16_t volatile *)CAN0_AM17L) /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN0_AM17L()         bfin_read16(CAN0_AM17L)
#define bfin_write_CAN0_AM17L(val)     bfin_write16(CAN0_AM17L, val)
#define pCAN0_AM17H                    ((uint16_t volatile *)CAN0_AM17H) /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM17H()         bfin_read16(CAN0_AM17H)
#define bfin_write_CAN0_AM17H(val)     bfin_write16(CAN0_AM17H, val)
#define pCAN0_AM18L                    ((uint16_t volatile *)CAN0_AM18L) /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN0_AM18L()         bfin_read16(CAN0_AM18L)
#define bfin_write_CAN0_AM18L(val)     bfin_write16(CAN0_AM18L, val)
#define pCAN0_AM18H                    ((uint16_t volatile *)CAN0_AM18H) /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM18H()         bfin_read16(CAN0_AM18H)
#define bfin_write_CAN0_AM18H(val)     bfin_write16(CAN0_AM18H, val)
#define pCAN0_AM19L                    ((uint16_t volatile *)CAN0_AM19L) /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN0_AM19L()         bfin_read16(CAN0_AM19L)
#define bfin_write_CAN0_AM19L(val)     bfin_write16(CAN0_AM19L, val)
#define pCAN0_AM19H                    ((uint16_t volatile *)CAN0_AM19H) /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM19H()         bfin_read16(CAN0_AM19H)
#define bfin_write_CAN0_AM19H(val)     bfin_write16(CAN0_AM19H, val)
#define pCAN0_AM20L                    ((uint16_t volatile *)CAN0_AM20L) /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN0_AM20L()         bfin_read16(CAN0_AM20L)
#define bfin_write_CAN0_AM20L(val)     bfin_write16(CAN0_AM20L, val)
#define pCAN0_AM20H                    ((uint16_t volatile *)CAN0_AM20H) /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM20H()         bfin_read16(CAN0_AM20H)
#define bfin_write_CAN0_AM20H(val)     bfin_write16(CAN0_AM20H, val)
#define pCAN0_AM21L                    ((uint16_t volatile *)CAN0_AM21L) /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN0_AM21L()         bfin_read16(CAN0_AM21L)
#define bfin_write_CAN0_AM21L(val)     bfin_write16(CAN0_AM21L, val)
#define pCAN0_AM21H                    ((uint16_t volatile *)CAN0_AM21H) /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM21H()         bfin_read16(CAN0_AM21H)
#define bfin_write_CAN0_AM21H(val)     bfin_write16(CAN0_AM21H, val)
#define pCAN0_AM22L                    ((uint16_t volatile *)CAN0_AM22L) /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN0_AM22L()         bfin_read16(CAN0_AM22L)
#define bfin_write_CAN0_AM22L(val)     bfin_write16(CAN0_AM22L, val)
#define pCAN0_AM22H                    ((uint16_t volatile *)CAN0_AM22H) /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM22H()         bfin_read16(CAN0_AM22H)
#define bfin_write_CAN0_AM22H(val)     bfin_write16(CAN0_AM22H, val)
#define pCAN0_AM23L                    ((uint16_t volatile *)CAN0_AM23L) /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN0_AM23L()         bfin_read16(CAN0_AM23L)
#define bfin_write_CAN0_AM23L(val)     bfin_write16(CAN0_AM23L, val)
#define pCAN0_AM23H                    ((uint16_t volatile *)CAN0_AM23H) /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM23H()         bfin_read16(CAN0_AM23H)
#define bfin_write_CAN0_AM23H(val)     bfin_write16(CAN0_AM23H, val)
#define pCAN0_AM24L                    ((uint16_t volatile *)CAN0_AM24L) /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN0_AM24L()         bfin_read16(CAN0_AM24L)
#define bfin_write_CAN0_AM24L(val)     bfin_write16(CAN0_AM24L, val)
#define pCAN0_AM24H                    ((uint16_t volatile *)CAN0_AM24H) /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM24H()         bfin_read16(CAN0_AM24H)
#define bfin_write_CAN0_AM24H(val)     bfin_write16(CAN0_AM24H, val)
#define pCAN0_AM25L                    ((uint16_t volatile *)CAN0_AM25L) /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN0_AM25L()         bfin_read16(CAN0_AM25L)
#define bfin_write_CAN0_AM25L(val)     bfin_write16(CAN0_AM25L, val)
#define pCAN0_AM25H                    ((uint16_t volatile *)CAN0_AM25H) /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM25H()         bfin_read16(CAN0_AM25H)
#define bfin_write_CAN0_AM25H(val)     bfin_write16(CAN0_AM25H, val)
#define pCAN0_AM26L                    ((uint16_t volatile *)CAN0_AM26L) /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN0_AM26L()         bfin_read16(CAN0_AM26L)
#define bfin_write_CAN0_AM26L(val)     bfin_write16(CAN0_AM26L, val)
#define pCAN0_AM26H                    ((uint16_t volatile *)CAN0_AM26H) /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM26H()         bfin_read16(CAN0_AM26H)
#define bfin_write_CAN0_AM26H(val)     bfin_write16(CAN0_AM26H, val)
#define pCAN0_AM27L                    ((uint16_t volatile *)CAN0_AM27L) /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN0_AM27L()         bfin_read16(CAN0_AM27L)
#define bfin_write_CAN0_AM27L(val)     bfin_write16(CAN0_AM27L, val)
#define pCAN0_AM27H                    ((uint16_t volatile *)CAN0_AM27H) /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM27H()         bfin_read16(CAN0_AM27H)
#define bfin_write_CAN0_AM27H(val)     bfin_write16(CAN0_AM27H, val)
#define pCAN0_AM28L                    ((uint16_t volatile *)CAN0_AM28L) /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN0_AM28L()         bfin_read16(CAN0_AM28L)
#define bfin_write_CAN0_AM28L(val)     bfin_write16(CAN0_AM28L, val)
#define pCAN0_AM28H                    ((uint16_t volatile *)CAN0_AM28H) /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM28H()         bfin_read16(CAN0_AM28H)
#define bfin_write_CAN0_AM28H(val)     bfin_write16(CAN0_AM28H, val)
#define pCAN0_AM29L                    ((uint16_t volatile *)CAN0_AM29L) /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN0_AM29L()         bfin_read16(CAN0_AM29L)
#define bfin_write_CAN0_AM29L(val)     bfin_write16(CAN0_AM29L, val)
#define pCAN0_AM29H                    ((uint16_t volatile *)CAN0_AM29H) /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM29H()         bfin_read16(CAN0_AM29H)
#define bfin_write_CAN0_AM29H(val)     bfin_write16(CAN0_AM29H, val)
#define pCAN0_AM30L                    ((uint16_t volatile *)CAN0_AM30L) /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN0_AM30L()         bfin_read16(CAN0_AM30L)
#define bfin_write_CAN0_AM30L(val)     bfin_write16(CAN0_AM30L, val)
#define pCAN0_AM30H                    ((uint16_t volatile *)CAN0_AM30H) /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM30H()         bfin_read16(CAN0_AM30H)
#define bfin_write_CAN0_AM30H(val)     bfin_write16(CAN0_AM30H, val)
#define pCAN0_AM31L                    ((uint16_t volatile *)CAN0_AM31L) /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN0_AM31L()         bfin_read16(CAN0_AM31L)
#define bfin_write_CAN0_AM31L(val)     bfin_write16(CAN0_AM31L, val)
#define pCAN0_AM31H                    ((uint16_t volatile *)CAN0_AM31H) /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN0_AM31H()         bfin_read16(CAN0_AM31H)
#define bfin_write_CAN0_AM31H(val)     bfin_write16(CAN0_AM31H, val)
#define pCAN0_MB00_DATA0               ((uint16_t volatile *)CAN0_MB00_DATA0) /* CAN Controller 0 Mailbox 0 Data 0 Register */
#define bfin_read_CAN0_MB00_DATA0()    bfin_read16(CAN0_MB00_DATA0)
#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
#define pCAN0_MB00_DATA1               ((uint16_t volatile *)CAN0_MB00_DATA1) /* CAN Controller 0 Mailbox 0 Data 1 Register */
#define bfin_read_CAN0_MB00_DATA1()    bfin_read16(CAN0_MB00_DATA1)
#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
#define pCAN0_MB00_DATA2               ((uint16_t volatile *)CAN0_MB00_DATA2) /* CAN Controller 0 Mailbox 0 Data 2 Register */
#define bfin_read_CAN0_MB00_DATA2()    bfin_read16(CAN0_MB00_DATA2)
#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
#define pCAN0_MB00_DATA3               ((uint16_t volatile *)CAN0_MB00_DATA3) /* CAN Controller 0 Mailbox 0 Data 3 Register */
#define bfin_read_CAN0_MB00_DATA3()    bfin_read16(CAN0_MB00_DATA3)
#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
#define pCAN0_MB00_LENGTH              ((uint16_t volatile *)CAN0_MB00_LENGTH) /* CAN Controller 0 Mailbox 0 Length Register */
#define bfin_read_CAN0_MB00_LENGTH()   bfin_read16(CAN0_MB00_LENGTH)
#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
#define pCAN0_MB00_TIMESTAMP           ((uint16_t volatile *)CAN0_MB00_TIMESTAMP) /* CAN Controller 0 Mailbox 0 Timestamp Register */
#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
#define pCAN0_MB00_ID0                 ((uint16_t volatile *)CAN0_MB00_ID0) /* CAN Controller 0 Mailbox 0 ID0 Register */
#define bfin_read_CAN0_MB00_ID0()      bfin_read16(CAN0_MB00_ID0)
#define bfin_write_CAN0_MB00_ID0(val)  bfin_write16(CAN0_MB00_ID0, val)
#define pCAN0_MB00_ID1                 ((uint16_t volatile *)CAN0_MB00_ID1) /* CAN Controller 0 Mailbox 0 ID1 Register */
#define bfin_read_CAN0_MB00_ID1()      bfin_read16(CAN0_MB00_ID1)
#define bfin_write_CAN0_MB00_ID1(val)  bfin_write16(CAN0_MB00_ID1, val)
#define pCAN0_MB01_DATA0               ((uint16_t volatile *)CAN0_MB01_DATA0) /* CAN Controller 0 Mailbox 1 Data 0 Register */
#define bfin_read_CAN0_MB01_DATA0()    bfin_read16(CAN0_MB01_DATA0)
#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
#define pCAN0_MB01_DATA1               ((uint16_t volatile *)CAN0_MB01_DATA1) /* CAN Controller 0 Mailbox 1 Data 1 Register */
#define bfin_read_CAN0_MB01_DATA1()    bfin_read16(CAN0_MB01_DATA1)
#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
#define pCAN0_MB01_DATA2               ((uint16_t volatile *)CAN0_MB01_DATA2) /* CAN Controller 0 Mailbox 1 Data 2 Register */
#define bfin_read_CAN0_MB01_DATA2()    bfin_read16(CAN0_MB01_DATA2)
#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
#define pCAN0_MB01_DATA3               ((uint16_t volatile *)CAN0_MB01_DATA3) /* CAN Controller 0 Mailbox 1 Data 3 Register */
#define bfin_read_CAN0_MB01_DATA3()    bfin_read16(CAN0_MB01_DATA3)
#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
#define pCAN0_MB01_LENGTH              ((uint16_t volatile *)CAN0_MB01_LENGTH) /* CAN Controller 0 Mailbox 1 Length Register */
#define bfin_read_CAN0_MB01_LENGTH()   bfin_read16(CAN0_MB01_LENGTH)
#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
#define pCAN0_MB01_TIMESTAMP           ((uint16_t volatile *)CAN0_MB01_TIMESTAMP) /* CAN Controller 0 Mailbox 1 Timestamp Register */
#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
#define pCAN0_MB01_ID0                 ((uint16_t volatile *)CAN0_MB01_ID0) /* CAN Controller 0 Mailbox 1 ID0 Register */
#define bfin_read_CAN0_MB01_ID0()      bfin_read16(CAN0_MB01_ID0)
#define bfin_write_CAN0_MB01_ID0(val)  bfin_write16(CAN0_MB01_ID0, val)
#define pCAN0_MB01_ID1                 ((uint16_t volatile *)CAN0_MB01_ID1) /* CAN Controller 0 Mailbox 1 ID1 Register */
#define bfin_read_CAN0_MB01_ID1()      bfin_read16(CAN0_MB01_ID1)
#define bfin_write_CAN0_MB01_ID1(val)  bfin_write16(CAN0_MB01_ID1, val)
#define pCAN0_MB02_DATA0               ((uint16_t volatile *)CAN0_MB02_DATA0) /* CAN Controller 0 Mailbox 2 Data 0 Register */
#define bfin_read_CAN0_MB02_DATA0()    bfin_read16(CAN0_MB02_DATA0)
#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
#define pCAN0_MB02_DATA1               ((uint16_t volatile *)CAN0_MB02_DATA1) /* CAN Controller 0 Mailbox 2 Data 1 Register */
#define bfin_read_CAN0_MB02_DATA1()    bfin_read16(CAN0_MB02_DATA1)
#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
#define pCAN0_MB02_DATA2               ((uint16_t volatile *)CAN0_MB02_DATA2) /* CAN Controller 0 Mailbox 2 Data 2 Register */
#define bfin_read_CAN0_MB02_DATA2()    bfin_read16(CAN0_MB02_DATA2)
#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
#define pCAN0_MB02_DATA3               ((uint16_t volatile *)CAN0_MB02_DATA3) /* CAN Controller 0 Mailbox 2 Data 3 Register */
#define bfin_read_CAN0_MB02_DATA3()    bfin_read16(CAN0_MB02_DATA3)
#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
#define pCAN0_MB02_LENGTH              ((uint16_t volatile *)CAN0_MB02_LENGTH) /* CAN Controller 0 Mailbox 2 Length Register */
#define bfin_read_CAN0_MB02_LENGTH()   bfin_read16(CAN0_MB02_LENGTH)
#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
#define pCAN0_MB02_TIMESTAMP           ((uint16_t volatile *)CAN0_MB02_TIMESTAMP) /* CAN Controller 0 Mailbox 2 Timestamp Register */
#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
#define pCAN0_MB02_ID0                 ((uint16_t volatile *)CAN0_MB02_ID0) /* CAN Controller 0 Mailbox 2 ID0 Register */
#define bfin_read_CAN0_MB02_ID0()      bfin_read16(CAN0_MB02_ID0)
#define bfin_write_CAN0_MB02_ID0(val)  bfin_write16(CAN0_MB02_ID0, val)
#define pCAN0_MB02_ID1                 ((uint16_t volatile *)CAN0_MB02_ID1) /* CAN Controller 0 Mailbox 2 ID1 Register */
#define bfin_read_CAN0_MB02_ID1()      bfin_read16(CAN0_MB02_ID1)
#define bfin_write_CAN0_MB02_ID1(val)  bfin_write16(CAN0_MB02_ID1, val)
#define pCAN0_MB03_DATA0               ((uint16_t volatile *)CAN0_MB03_DATA0) /* CAN Controller 0 Mailbox 3 Data 0 Register */
#define bfin_read_CAN0_MB03_DATA0()    bfin_read16(CAN0_MB03_DATA0)
#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
#define pCAN0_MB03_DATA1               ((uint16_t volatile *)CAN0_MB03_DATA1) /* CAN Controller 0 Mailbox 3 Data 1 Register */
#define bfin_read_CAN0_MB03_DATA1()    bfin_read16(CAN0_MB03_DATA1)
#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
#define pCAN0_MB03_DATA2               ((uint16_t volatile *)CAN0_MB03_DATA2) /* CAN Controller 0 Mailbox 3 Data 2 Register */
#define bfin_read_CAN0_MB03_DATA2()    bfin_read16(CAN0_MB03_DATA2)
#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
#define pCAN0_MB03_DATA3               ((uint16_t volatile *)CAN0_MB03_DATA3) /* CAN Controller 0 Mailbox 3 Data 3 Register */
#define bfin_read_CAN0_MB03_DATA3()    bfin_read16(CAN0_MB03_DATA3)
#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
#define pCAN0_MB03_LENGTH              ((uint16_t volatile *)CAN0_MB03_LENGTH) /* CAN Controller 0 Mailbox 3 Length Register */
#define bfin_read_CAN0_MB03_LENGTH()   bfin_read16(CAN0_MB03_LENGTH)
#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
#define pCAN0_MB03_TIMESTAMP           ((uint16_t volatile *)CAN0_MB03_TIMESTAMP) /* CAN Controller 0 Mailbox 3 Timestamp Register */
#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
#define pCAN0_MB03_ID0                 ((uint16_t volatile *)CAN0_MB03_ID0) /* CAN Controller 0 Mailbox 3 ID0 Register */
#define bfin_read_CAN0_MB03_ID0()      bfin_read16(CAN0_MB03_ID0)
#define bfin_write_CAN0_MB03_ID0(val)  bfin_write16(CAN0_MB03_ID0, val)
#define pCAN0_MB03_ID1                 ((uint16_t volatile *)CAN0_MB03_ID1) /* CAN Controller 0 Mailbox 3 ID1 Register */
#define bfin_read_CAN0_MB03_ID1()      bfin_read16(CAN0_MB03_ID1)
#define bfin_write_CAN0_MB03_ID1(val)  bfin_write16(CAN0_MB03_ID1, val)
#define pCAN0_MB04_DATA0               ((uint16_t volatile *)CAN0_MB04_DATA0) /* CAN Controller 0 Mailbox 4 Data 0 Register */
#define bfin_read_CAN0_MB04_DATA0()    bfin_read16(CAN0_MB04_DATA0)
#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
#define pCAN0_MB04_DATA1               ((uint16_t volatile *)CAN0_MB04_DATA1) /* CAN Controller 0 Mailbox 4 Data 1 Register */
#define bfin_read_CAN0_MB04_DATA1()    bfin_read16(CAN0_MB04_DATA1)
#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
#define pCAN0_MB04_DATA2               ((uint16_t volatile *)CAN0_MB04_DATA2) /* CAN Controller 0 Mailbox 4 Data 2 Register */
#define bfin_read_CAN0_MB04_DATA2()    bfin_read16(CAN0_MB04_DATA2)
#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
#define pCAN0_MB04_DATA3               ((uint16_t volatile *)CAN0_MB04_DATA3) /* CAN Controller 0 Mailbox 4 Data 3 Register */
#define bfin_read_CAN0_MB04_DATA3()    bfin_read16(CAN0_MB04_DATA3)
#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
#define pCAN0_MB04_LENGTH              ((uint16_t volatile *)CAN0_MB04_LENGTH) /* CAN Controller 0 Mailbox 4 Length Register */
#define bfin_read_CAN0_MB04_LENGTH()   bfin_read16(CAN0_MB04_LENGTH)
#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
#define pCAN0_MB04_TIMESTAMP           ((uint16_t volatile *)CAN0_MB04_TIMESTAMP) /* CAN Controller 0 Mailbox 4 Timestamp Register */
#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
#define pCAN0_MB04_ID0                 ((uint16_t volatile *)CAN0_MB04_ID0) /* CAN Controller 0 Mailbox 4 ID0 Register */
#define bfin_read_CAN0_MB04_ID0()      bfin_read16(CAN0_MB04_ID0)
#define bfin_write_CAN0_MB04_ID0(val)  bfin_write16(CAN0_MB04_ID0, val)
#define pCAN0_MB04_ID1                 ((uint16_t volatile *)CAN0_MB04_ID1) /* CAN Controller 0 Mailbox 4 ID1 Register */
#define bfin_read_CAN0_MB04_ID1()      bfin_read16(CAN0_MB04_ID1)
#define bfin_write_CAN0_MB04_ID1(val)  bfin_write16(CAN0_MB04_ID1, val)
#define pCAN0_MB05_DATA0               ((uint16_t volatile *)CAN0_MB05_DATA0) /* CAN Controller 0 Mailbox 5 Data 0 Register */
#define bfin_read_CAN0_MB05_DATA0()    bfin_read16(CAN0_MB05_DATA0)
#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
#define pCAN0_MB05_DATA1               ((uint16_t volatile *)CAN0_MB05_DATA1) /* CAN Controller 0 Mailbox 5 Data 1 Register */
#define bfin_read_CAN0_MB05_DATA1()    bfin_read16(CAN0_MB05_DATA1)
#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
#define pCAN0_MB05_DATA2               ((uint16_t volatile *)CAN0_MB05_DATA2) /* CAN Controller 0 Mailbox 5 Data 2 Register */
#define bfin_read_CAN0_MB05_DATA2()    bfin_read16(CAN0_MB05_DATA2)
#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
#define pCAN0_MB05_DATA3               ((uint16_t volatile *)CAN0_MB05_DATA3) /* CAN Controller 0 Mailbox 5 Data 3 Register */
#define bfin_read_CAN0_MB05_DATA3()    bfin_read16(CAN0_MB05_DATA3)
#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
#define pCAN0_MB05_LENGTH              ((uint16_t volatile *)CAN0_MB05_LENGTH) /* CAN Controller 0 Mailbox 5 Length Register */
#define bfin_read_CAN0_MB05_LENGTH()   bfin_read16(CAN0_MB05_LENGTH)
#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
#define pCAN0_MB05_TIMESTAMP           ((uint16_t volatile *)CAN0_MB05_TIMESTAMP) /* CAN Controller 0 Mailbox 5 Timestamp Register */
#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
#define pCAN0_MB05_ID0                 ((uint16_t volatile *)CAN0_MB05_ID0) /* CAN Controller 0 Mailbox 5 ID0 Register */
#define bfin_read_CAN0_MB05_ID0()      bfin_read16(CAN0_MB05_ID0)
#define bfin_write_CAN0_MB05_ID0(val)  bfin_write16(CAN0_MB05_ID0, val)
#define pCAN0_MB05_ID1                 ((uint16_t volatile *)CAN0_MB05_ID1) /* CAN Controller 0 Mailbox 5 ID1 Register */
#define bfin_read_CAN0_MB05_ID1()      bfin_read16(CAN0_MB05_ID1)
#define bfin_write_CAN0_MB05_ID1(val)  bfin_write16(CAN0_MB05_ID1, val)
#define pCAN0_MB06_DATA0               ((uint16_t volatile *)CAN0_MB06_DATA0) /* CAN Controller 0 Mailbox 6 Data 0 Register */
#define bfin_read_CAN0_MB06_DATA0()    bfin_read16(CAN0_MB06_DATA0)
#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
#define pCAN0_MB06_DATA1               ((uint16_t volatile *)CAN0_MB06_DATA1) /* CAN Controller 0 Mailbox 6 Data 1 Register */
#define bfin_read_CAN0_MB06_DATA1()    bfin_read16(CAN0_MB06_DATA1)
#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
#define pCAN0_MB06_DATA2               ((uint16_t volatile *)CAN0_MB06_DATA2) /* CAN Controller 0 Mailbox 6 Data 2 Register */
#define bfin_read_CAN0_MB06_DATA2()    bfin_read16(CAN0_MB06_DATA2)
#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
#define pCAN0_MB06_DATA3               ((uint16_t volatile *)CAN0_MB06_DATA3) /* CAN Controller 0 Mailbox 6 Data 3 Register */
#define bfin_read_CAN0_MB06_DATA3()    bfin_read16(CAN0_MB06_DATA3)
#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
#define pCAN0_MB06_LENGTH              ((uint16_t volatile *)CAN0_MB06_LENGTH) /* CAN Controller 0 Mailbox 6 Length Register */
#define bfin_read_CAN0_MB06_LENGTH()   bfin_read16(CAN0_MB06_LENGTH)
#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
#define pCAN0_MB06_TIMESTAMP           ((uint16_t volatile *)CAN0_MB06_TIMESTAMP) /* CAN Controller 0 Mailbox 6 Timestamp Register */
#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
#define pCAN0_MB06_ID0                 ((uint16_t volatile *)CAN0_MB06_ID0) /* CAN Controller 0 Mailbox 6 ID0 Register */
#define bfin_read_CAN0_MB06_ID0()      bfin_read16(CAN0_MB06_ID0)
#define bfin_write_CAN0_MB06_ID0(val)  bfin_write16(CAN0_MB06_ID0, val)
#define pCAN0_MB06_ID1                 ((uint16_t volatile *)CAN0_MB06_ID1) /* CAN Controller 0 Mailbox 6 ID1 Register */
#define bfin_read_CAN0_MB06_ID1()      bfin_read16(CAN0_MB06_ID1)
#define bfin_write_CAN0_MB06_ID1(val)  bfin_write16(CAN0_MB06_ID1, val)
#define pCAN0_MB07_DATA0               ((uint16_t volatile *)CAN0_MB07_DATA0) /* CAN Controller 0 Mailbox 7 Data 0 Register */
#define bfin_read_CAN0_MB07_DATA0()    bfin_read16(CAN0_MB07_DATA0)
#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
#define pCAN0_MB07_DATA1               ((uint16_t volatile *)CAN0_MB07_DATA1) /* CAN Controller 0 Mailbox 7 Data 1 Register */
#define bfin_read_CAN0_MB07_DATA1()    bfin_read16(CAN0_MB07_DATA1)
#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
#define pCAN0_MB07_DATA2               ((uint16_t volatile *)CAN0_MB07_DATA2) /* CAN Controller 0 Mailbox 7 Data 2 Register */
#define bfin_read_CAN0_MB07_DATA2()    bfin_read16(CAN0_MB07_DATA2)
#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
#define pCAN0_MB07_DATA3               ((uint16_t volatile *)CAN0_MB07_DATA3) /* CAN Controller 0 Mailbox 7 Data 3 Register */
#define bfin_read_CAN0_MB07_DATA3()    bfin_read16(CAN0_MB07_DATA3)
#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
#define pCAN0_MB07_LENGTH              ((uint16_t volatile *)CAN0_MB07_LENGTH) /* CAN Controller 0 Mailbox 7 Length Register */
#define bfin_read_CAN0_MB07_LENGTH()   bfin_read16(CAN0_MB07_LENGTH)
#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
#define pCAN0_MB07_TIMESTAMP           ((uint16_t volatile *)CAN0_MB07_TIMESTAMP) /* CAN Controller 0 Mailbox 7 Timestamp Register */
#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
#define pCAN0_MB07_ID0                 ((uint16_t volatile *)CAN0_MB07_ID0) /* CAN Controller 0 Mailbox 7 ID0 Register */
#define bfin_read_CAN0_MB07_ID0()      bfin_read16(CAN0_MB07_ID0)
#define bfin_write_CAN0_MB07_ID0(val)  bfin_write16(CAN0_MB07_ID0, val)
#define pCAN0_MB07_ID1                 ((uint16_t volatile *)CAN0_MB07_ID1) /* CAN Controller 0 Mailbox 7 ID1 Register */
#define bfin_read_CAN0_MB07_ID1()      bfin_read16(CAN0_MB07_ID1)
#define bfin_write_CAN0_MB07_ID1(val)  bfin_write16(CAN0_MB07_ID1, val)
#define pCAN0_MB08_DATA0               ((uint16_t volatile *)CAN0_MB08_DATA0) /* CAN Controller 0 Mailbox 8 Data 0 Register */
#define bfin_read_CAN0_MB08_DATA0()    bfin_read16(CAN0_MB08_DATA0)
#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
#define pCAN0_MB08_DATA1               ((uint16_t volatile *)CAN0_MB08_DATA1) /* CAN Controller 0 Mailbox 8 Data 1 Register */
#define bfin_read_CAN0_MB08_DATA1()    bfin_read16(CAN0_MB08_DATA1)
#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
#define pCAN0_MB08_DATA2               ((uint16_t volatile *)CAN0_MB08_DATA2) /* CAN Controller 0 Mailbox 8 Data 2 Register */
#define bfin_read_CAN0_MB08_DATA2()    bfin_read16(CAN0_MB08_DATA2)
#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
#define pCAN0_MB08_DATA3               ((uint16_t volatile *)CAN0_MB08_DATA3) /* CAN Controller 0 Mailbox 8 Data 3 Register */
#define bfin_read_CAN0_MB08_DATA3()    bfin_read16(CAN0_MB08_DATA3)
#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
#define pCAN0_MB08_LENGTH              ((uint16_t volatile *)CAN0_MB08_LENGTH) /* CAN Controller 0 Mailbox 8 Length Register */
#define bfin_read_CAN0_MB08_LENGTH()   bfin_read16(CAN0_MB08_LENGTH)
#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
#define pCAN0_MB08_TIMESTAMP           ((uint16_t volatile *)CAN0_MB08_TIMESTAMP) /* CAN Controller 0 Mailbox 8 Timestamp Register */
#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
#define pCAN0_MB08_ID0                 ((uint16_t volatile *)CAN0_MB08_ID0) /* CAN Controller 0 Mailbox 8 ID0 Register */
#define bfin_read_CAN0_MB08_ID0()      bfin_read16(CAN0_MB08_ID0)
#define bfin_write_CAN0_MB08_ID0(val)  bfin_write16(CAN0_MB08_ID0, val)
#define pCAN0_MB08_ID1                 ((uint16_t volatile *)CAN0_MB08_ID1) /* CAN Controller 0 Mailbox 8 ID1 Register */
#define bfin_read_CAN0_MB08_ID1()      bfin_read16(CAN0_MB08_ID1)
#define bfin_write_CAN0_MB08_ID1(val)  bfin_write16(CAN0_MB08_ID1, val)
#define pCAN0_MB09_DATA0               ((uint16_t volatile *)CAN0_MB09_DATA0) /* CAN Controller 0 Mailbox 9 Data 0 Register */
#define bfin_read_CAN0_MB09_DATA0()    bfin_read16(CAN0_MB09_DATA0)
#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
#define pCAN0_MB09_DATA1               ((uint16_t volatile *)CAN0_MB09_DATA1) /* CAN Controller 0 Mailbox 9 Data 1 Register */
#define bfin_read_CAN0_MB09_DATA1()    bfin_read16(CAN0_MB09_DATA1)
#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
#define pCAN0_MB09_DATA2               ((uint16_t volatile *)CAN0_MB09_DATA2) /* CAN Controller 0 Mailbox 9 Data 2 Register */
#define bfin_read_CAN0_MB09_DATA2()    bfin_read16(CAN0_MB09_DATA2)
#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
#define pCAN0_MB09_DATA3               ((uint16_t volatile *)CAN0_MB09_DATA3) /* CAN Controller 0 Mailbox 9 Data 3 Register */
#define bfin_read_CAN0_MB09_DATA3()    bfin_read16(CAN0_MB09_DATA3)
#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
#define pCAN0_MB09_LENGTH              ((uint16_t volatile *)CAN0_MB09_LENGTH) /* CAN Controller 0 Mailbox 9 Length Register */
#define bfin_read_CAN0_MB09_LENGTH()   bfin_read16(CAN0_MB09_LENGTH)
#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
#define pCAN0_MB09_TIMESTAMP           ((uint16_t volatile *)CAN0_MB09_TIMESTAMP) /* CAN Controller 0 Mailbox 9 Timestamp Register */
#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
#define pCAN0_MB09_ID0                 ((uint16_t volatile *)CAN0_MB09_ID0) /* CAN Controller 0 Mailbox 9 ID0 Register */
#define bfin_read_CAN0_MB09_ID0()      bfin_read16(CAN0_MB09_ID0)
#define bfin_write_CAN0_MB09_ID0(val)  bfin_write16(CAN0_MB09_ID0, val)
#define pCAN0_MB09_ID1                 ((uint16_t volatile *)CAN0_MB09_ID1) /* CAN Controller 0 Mailbox 9 ID1 Register */
#define bfin_read_CAN0_MB09_ID1()      bfin_read16(CAN0_MB09_ID1)
#define bfin_write_CAN0_MB09_ID1(val)  bfin_write16(CAN0_MB09_ID1, val)
#define pCAN0_MB10_DATA0               ((uint16_t volatile *)CAN0_MB10_DATA0) /* CAN Controller 0 Mailbox 10 Data 0 Register */
#define bfin_read_CAN0_MB10_DATA0()    bfin_read16(CAN0_MB10_DATA0)
#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
#define pCAN0_MB10_DATA1               ((uint16_t volatile *)CAN0_MB10_DATA1) /* CAN Controller 0 Mailbox 10 Data 1 Register */
#define bfin_read_CAN0_MB10_DATA1()    bfin_read16(CAN0_MB10_DATA1)
#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
#define pCAN0_MB10_DATA2               ((uint16_t volatile *)CAN0_MB10_DATA2) /* CAN Controller 0 Mailbox 10 Data 2 Register */
#define bfin_read_CAN0_MB10_DATA2()    bfin_read16(CAN0_MB10_DATA2)
#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
#define pCAN0_MB10_DATA3               ((uint16_t volatile *)CAN0_MB10_DATA3) /* CAN Controller 0 Mailbox 10 Data 3 Register */
#define bfin_read_CAN0_MB10_DATA3()    bfin_read16(CAN0_MB10_DATA3)
#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
#define pCAN0_MB10_LENGTH              ((uint16_t volatile *)CAN0_MB10_LENGTH) /* CAN Controller 0 Mailbox 10 Length Register */
#define bfin_read_CAN0_MB10_LENGTH()   bfin_read16(CAN0_MB10_LENGTH)
#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
#define pCAN0_MB10_TIMESTAMP           ((uint16_t volatile *)CAN0_MB10_TIMESTAMP) /* CAN Controller 0 Mailbox 10 Timestamp Register */
#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
#define pCAN0_MB10_ID0                 ((uint16_t volatile *)CAN0_MB10_ID0) /* CAN Controller 0 Mailbox 10 ID0 Register */
#define bfin_read_CAN0_MB10_ID0()      bfin_read16(CAN0_MB10_ID0)
#define bfin_write_CAN0_MB10_ID0(val)  bfin_write16(CAN0_MB10_ID0, val)
#define pCAN0_MB10_ID1                 ((uint16_t volatile *)CAN0_MB10_ID1) /* CAN Controller 0 Mailbox 10 ID1 Register */
#define bfin_read_CAN0_MB10_ID1()      bfin_read16(CAN0_MB10_ID1)
#define bfin_write_CAN0_MB10_ID1(val)  bfin_write16(CAN0_MB10_ID1, val)
#define pCAN0_MB11_DATA0               ((uint16_t volatile *)CAN0_MB11_DATA0) /* CAN Controller 0 Mailbox 11 Data 0 Register */
#define bfin_read_CAN0_MB11_DATA0()    bfin_read16(CAN0_MB11_DATA0)
#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
#define pCAN0_MB11_DATA1               ((uint16_t volatile *)CAN0_MB11_DATA1) /* CAN Controller 0 Mailbox 11 Data 1 Register */
#define bfin_read_CAN0_MB11_DATA1()    bfin_read16(CAN0_MB11_DATA1)
#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
#define pCAN0_MB11_DATA2               ((uint16_t volatile *)CAN0_MB11_DATA2) /* CAN Controller 0 Mailbox 11 Data 2 Register */
#define bfin_read_CAN0_MB11_DATA2()    bfin_read16(CAN0_MB11_DATA2)
#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
#define pCAN0_MB11_DATA3               ((uint16_t volatile *)CAN0_MB11_DATA3) /* CAN Controller 0 Mailbox 11 Data 3 Register */
#define bfin_read_CAN0_MB11_DATA3()    bfin_read16(CAN0_MB11_DATA3)
#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
#define pCAN0_MB11_LENGTH              ((uint16_t volatile *)CAN0_MB11_LENGTH) /* CAN Controller 0 Mailbox 11 Length Register */
#define bfin_read_CAN0_MB11_LENGTH()   bfin_read16(CAN0_MB11_LENGTH)
#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
#define pCAN0_MB11_TIMESTAMP           ((uint16_t volatile *)CAN0_MB11_TIMESTAMP) /* CAN Controller 0 Mailbox 11 Timestamp Register */
#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
#define pCAN0_MB11_ID0                 ((uint16_t volatile *)CAN0_MB11_ID0) /* CAN Controller 0 Mailbox 11 ID0 Register */
#define bfin_read_CAN0_MB11_ID0()      bfin_read16(CAN0_MB11_ID0)
#define bfin_write_CAN0_MB11_ID0(val)  bfin_write16(CAN0_MB11_ID0, val)
#define pCAN0_MB11_ID1                 ((uint16_t volatile *)CAN0_MB11_ID1) /* CAN Controller 0 Mailbox 11 ID1 Register */
#define bfin_read_CAN0_MB11_ID1()      bfin_read16(CAN0_MB11_ID1)
#define bfin_write_CAN0_MB11_ID1(val)  bfin_write16(CAN0_MB11_ID1, val)
#define pCAN0_MB12_DATA0               ((uint16_t volatile *)CAN0_MB12_DATA0) /* CAN Controller 0 Mailbox 12 Data 0 Register */
#define bfin_read_CAN0_MB12_DATA0()    bfin_read16(CAN0_MB12_DATA0)
#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
#define pCAN0_MB12_DATA1               ((uint16_t volatile *)CAN0_MB12_DATA1) /* CAN Controller 0 Mailbox 12 Data 1 Register */
#define bfin_read_CAN0_MB12_DATA1()    bfin_read16(CAN0_MB12_DATA1)
#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
#define pCAN0_MB12_DATA2               ((uint16_t volatile *)CAN0_MB12_DATA2) /* CAN Controller 0 Mailbox 12 Data 2 Register */
#define bfin_read_CAN0_MB12_DATA2()    bfin_read16(CAN0_MB12_DATA2)
#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
#define pCAN0_MB12_DATA3               ((uint16_t volatile *)CAN0_MB12_DATA3) /* CAN Controller 0 Mailbox 12 Data 3 Register */
#define bfin_read_CAN0_MB12_DATA3()    bfin_read16(CAN0_MB12_DATA3)
#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
#define pCAN0_MB12_LENGTH              ((uint16_t volatile *)CAN0_MB12_LENGTH) /* CAN Controller 0 Mailbox 12 Length Register */
#define bfin_read_CAN0_MB12_LENGTH()   bfin_read16(CAN0_MB12_LENGTH)
#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
#define pCAN0_MB12_TIMESTAMP           ((uint16_t volatile *)CAN0_MB12_TIMESTAMP) /* CAN Controller 0 Mailbox 12 Timestamp Register */
#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
#define pCAN0_MB12_ID0                 ((uint16_t volatile *)CAN0_MB12_ID0) /* CAN Controller 0 Mailbox 12 ID0 Register */
#define bfin_read_CAN0_MB12_ID0()      bfin_read16(CAN0_MB12_ID0)
#define bfin_write_CAN0_MB12_ID0(val)  bfin_write16(CAN0_MB12_ID0, val)
#define pCAN0_MB12_ID1                 ((uint16_t volatile *)CAN0_MB12_ID1) /* CAN Controller 0 Mailbox 12 ID1 Register */
#define bfin_read_CAN0_MB12_ID1()      bfin_read16(CAN0_MB12_ID1)
#define bfin_write_CAN0_MB12_ID1(val)  bfin_write16(CAN0_MB12_ID1, val)
#define pCAN0_MB13_DATA0               ((uint16_t volatile *)CAN0_MB13_DATA0) /* CAN Controller 0 Mailbox 13 Data 0 Register */
#define bfin_read_CAN0_MB13_DATA0()    bfin_read16(CAN0_MB13_DATA0)
#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
#define pCAN0_MB13_DATA1               ((uint16_t volatile *)CAN0_MB13_DATA1) /* CAN Controller 0 Mailbox 13 Data 1 Register */
#define bfin_read_CAN0_MB13_DATA1()    bfin_read16(CAN0_MB13_DATA1)
#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
#define pCAN0_MB13_DATA2               ((uint16_t volatile *)CAN0_MB13_DATA2) /* CAN Controller 0 Mailbox 13 Data 2 Register */
#define bfin_read_CAN0_MB13_DATA2()    bfin_read16(CAN0_MB13_DATA2)
#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
#define pCAN0_MB13_DATA3               ((uint16_t volatile *)CAN0_MB13_DATA3) /* CAN Controller 0 Mailbox 13 Data 3 Register */
#define bfin_read_CAN0_MB13_DATA3()    bfin_read16(CAN0_MB13_DATA3)
#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
#define pCAN0_MB13_LENGTH              ((uint16_t volatile *)CAN0_MB13_LENGTH) /* CAN Controller 0 Mailbox 13 Length Register */
#define bfin_read_CAN0_MB13_LENGTH()   bfin_read16(CAN0_MB13_LENGTH)
#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
#define pCAN0_MB13_TIMESTAMP           ((uint16_t volatile *)CAN0_MB13_TIMESTAMP) /* CAN Controller 0 Mailbox 13 Timestamp Register */
#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
#define pCAN0_MB13_ID0                 ((uint16_t volatile *)CAN0_MB13_ID0) /* CAN Controller 0 Mailbox 13 ID0 Register */
#define bfin_read_CAN0_MB13_ID0()      bfin_read16(CAN0_MB13_ID0)
#define bfin_write_CAN0_MB13_ID0(val)  bfin_write16(CAN0_MB13_ID0, val)
#define pCAN0_MB13_ID1                 ((uint16_t volatile *)CAN0_MB13_ID1) /* CAN Controller 0 Mailbox 13 ID1 Register */
#define bfin_read_CAN0_MB13_ID1()      bfin_read16(CAN0_MB13_ID1)
#define bfin_write_CAN0_MB13_ID1(val)  bfin_write16(CAN0_MB13_ID1, val)
#define pCAN0_MB14_DATA0               ((uint16_t volatile *)CAN0_MB14_DATA0) /* CAN Controller 0 Mailbox 14 Data 0 Register */
#define bfin_read_CAN0_MB14_DATA0()    bfin_read16(CAN0_MB14_DATA0)
#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
#define pCAN0_MB14_DATA1               ((uint16_t volatile *)CAN0_MB14_DATA1) /* CAN Controller 0 Mailbox 14 Data 1 Register */
#define bfin_read_CAN0_MB14_DATA1()    bfin_read16(CAN0_MB14_DATA1)
#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
#define pCAN0_MB14_DATA2               ((uint16_t volatile *)CAN0_MB14_DATA2) /* CAN Controller 0 Mailbox 14 Data 2 Register */
#define bfin_read_CAN0_MB14_DATA2()    bfin_read16(CAN0_MB14_DATA2)
#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
#define pCAN0_MB14_DATA3               ((uint16_t volatile *)CAN0_MB14_DATA3) /* CAN Controller 0 Mailbox 14 Data 3 Register */
#define bfin_read_CAN0_MB14_DATA3()    bfin_read16(CAN0_MB14_DATA3)
#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
#define pCAN0_MB14_LENGTH              ((uint16_t volatile *)CAN0_MB14_LENGTH) /* CAN Controller 0 Mailbox 14 Length Register */
#define bfin_read_CAN0_MB14_LENGTH()   bfin_read16(CAN0_MB14_LENGTH)
#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
#define pCAN0_MB14_TIMESTAMP           ((uint16_t volatile *)CAN0_MB14_TIMESTAMP) /* CAN Controller 0 Mailbox 14 Timestamp Register */
#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
#define pCAN0_MB14_ID0                 ((uint16_t volatile *)CAN0_MB14_ID0) /* CAN Controller 0 Mailbox 14 ID0 Register */
#define bfin_read_CAN0_MB14_ID0()      bfin_read16(CAN0_MB14_ID0)
#define bfin_write_CAN0_MB14_ID0(val)  bfin_write16(CAN0_MB14_ID0, val)
#define pCAN0_MB14_ID1                 ((uint16_t volatile *)CAN0_MB14_ID1) /* CAN Controller 0 Mailbox 14 ID1 Register */
#define bfin_read_CAN0_MB14_ID1()      bfin_read16(CAN0_MB14_ID1)
#define bfin_write_CAN0_MB14_ID1(val)  bfin_write16(CAN0_MB14_ID1, val)
#define pCAN0_MB15_DATA0               ((uint16_t volatile *)CAN0_MB15_DATA0) /* CAN Controller 0 Mailbox 15 Data 0 Register */
#define bfin_read_CAN0_MB15_DATA0()    bfin_read16(CAN0_MB15_DATA0)
#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
#define pCAN0_MB15_DATA1               ((uint16_t volatile *)CAN0_MB15_DATA1) /* CAN Controller 0 Mailbox 15 Data 1 Register */
#define bfin_read_CAN0_MB15_DATA1()    bfin_read16(CAN0_MB15_DATA1)
#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
#define pCAN0_MB15_DATA2               ((uint16_t volatile *)CAN0_MB15_DATA2) /* CAN Controller 0 Mailbox 15 Data 2 Register */
#define bfin_read_CAN0_MB15_DATA2()    bfin_read16(CAN0_MB15_DATA2)
#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
#define pCAN0_MB15_DATA3               ((uint16_t volatile *)CAN0_MB15_DATA3) /* CAN Controller 0 Mailbox 15 Data 3 Register */
#define bfin_read_CAN0_MB15_DATA3()    bfin_read16(CAN0_MB15_DATA3)
#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
#define pCAN0_MB15_LENGTH              ((uint16_t volatile *)CAN0_MB15_LENGTH) /* CAN Controller 0 Mailbox 15 Length Register */
#define bfin_read_CAN0_MB15_LENGTH()   bfin_read16(CAN0_MB15_LENGTH)
#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
#define pCAN0_MB15_TIMESTAMP           ((uint16_t volatile *)CAN0_MB15_TIMESTAMP) /* CAN Controller 0 Mailbox 15 Timestamp Register */
#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
#define pCAN0_MB15_ID0                 ((uint16_t volatile *)CAN0_MB15_ID0) /* CAN Controller 0 Mailbox 15 ID0 Register */
#define bfin_read_CAN0_MB15_ID0()      bfin_read16(CAN0_MB15_ID0)
#define bfin_write_CAN0_MB15_ID0(val)  bfin_write16(CAN0_MB15_ID0, val)
#define pCAN0_MB15_ID1                 ((uint16_t volatile *)CAN0_MB15_ID1) /* CAN Controller 0 Mailbox 15 ID1 Register */
#define bfin_read_CAN0_MB15_ID1()      bfin_read16(CAN0_MB15_ID1)
#define bfin_write_CAN0_MB15_ID1(val)  bfin_write16(CAN0_MB15_ID1, val)
#define pCAN0_MB16_DATA0               ((uint16_t volatile *)CAN0_MB16_DATA0) /* CAN Controller 0 Mailbox 16 Data 0 Register */
#define bfin_read_CAN0_MB16_DATA0()    bfin_read16(CAN0_MB16_DATA0)
#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
#define pCAN0_MB16_DATA1               ((uint16_t volatile *)CAN0_MB16_DATA1) /* CAN Controller 0 Mailbox 16 Data 1 Register */
#define bfin_read_CAN0_MB16_DATA1()    bfin_read16(CAN0_MB16_DATA1)
#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
#define pCAN0_MB16_DATA2               ((uint16_t volatile *)CAN0_MB16_DATA2) /* CAN Controller 0 Mailbox 16 Data 2 Register */
#define bfin_read_CAN0_MB16_DATA2()    bfin_read16(CAN0_MB16_DATA2)
#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
#define pCAN0_MB16_DATA3               ((uint16_t volatile *)CAN0_MB16_DATA3) /* CAN Controller 0 Mailbox 16 Data 3 Register */
#define bfin_read_CAN0_MB16_DATA3()    bfin_read16(CAN0_MB16_DATA3)
#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
#define pCAN0_MB16_LENGTH              ((uint16_t volatile *)CAN0_MB16_LENGTH) /* CAN Controller 0 Mailbox 16 Length Register */
#define bfin_read_CAN0_MB16_LENGTH()   bfin_read16(CAN0_MB16_LENGTH)
#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
#define pCAN0_MB16_TIMESTAMP           ((uint16_t volatile *)CAN0_MB16_TIMESTAMP) /* CAN Controller 0 Mailbox 16 Timestamp Register */
#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
#define pCAN0_MB16_ID0                 ((uint16_t volatile *)CAN0_MB16_ID0) /* CAN Controller 0 Mailbox 16 ID0 Register */
#define bfin_read_CAN0_MB16_ID0()      bfin_read16(CAN0_MB16_ID0)
#define bfin_write_CAN0_MB16_ID0(val)  bfin_write16(CAN0_MB16_ID0, val)
#define pCAN0_MB16_ID1                 ((uint16_t volatile *)CAN0_MB16_ID1) /* CAN Controller 0 Mailbox 16 ID1 Register */
#define bfin_read_CAN0_MB16_ID1()      bfin_read16(CAN0_MB16_ID1)
#define bfin_write_CAN0_MB16_ID1(val)  bfin_write16(CAN0_MB16_ID1, val)
#define pCAN0_MB17_DATA0               ((uint16_t volatile *)CAN0_MB17_DATA0) /* CAN Controller 0 Mailbox 17 Data 0 Register */
#define bfin_read_CAN0_MB17_DATA0()    bfin_read16(CAN0_MB17_DATA0)
#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
#define pCAN0_MB17_DATA1               ((uint16_t volatile *)CAN0_MB17_DATA1) /* CAN Controller 0 Mailbox 17 Data 1 Register */
#define bfin_read_CAN0_MB17_DATA1()    bfin_read16(CAN0_MB17_DATA1)
#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
#define pCAN0_MB17_DATA2               ((uint16_t volatile *)CAN0_MB17_DATA2) /* CAN Controller 0 Mailbox 17 Data 2 Register */
#define bfin_read_CAN0_MB17_DATA2()    bfin_read16(CAN0_MB17_DATA2)
#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
#define pCAN0_MB17_DATA3               ((uint16_t volatile *)CAN0_MB17_DATA3) /* CAN Controller 0 Mailbox 17 Data 3 Register */
#define bfin_read_CAN0_MB17_DATA3()    bfin_read16(CAN0_MB17_DATA3)
#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
#define pCAN0_MB17_LENGTH              ((uint16_t volatile *)CAN0_MB17_LENGTH) /* CAN Controller 0 Mailbox 17 Length Register */
#define bfin_read_CAN0_MB17_LENGTH()   bfin_read16(CAN0_MB17_LENGTH)
#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
#define pCAN0_MB17_TIMESTAMP           ((uint16_t volatile *)CAN0_MB17_TIMESTAMP) /* CAN Controller 0 Mailbox 17 Timestamp Register */
#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
#define pCAN0_MB17_ID0                 ((uint16_t volatile *)CAN0_MB17_ID0) /* CAN Controller 0 Mailbox 17 ID0 Register */
#define bfin_read_CAN0_MB17_ID0()      bfin_read16(CAN0_MB17_ID0)
#define bfin_write_CAN0_MB17_ID0(val)  bfin_write16(CAN0_MB17_ID0, val)
#define pCAN0_MB17_ID1                 ((uint16_t volatile *)CAN0_MB17_ID1) /* CAN Controller 0 Mailbox 17 ID1 Register */
#define bfin_read_CAN0_MB17_ID1()      bfin_read16(CAN0_MB17_ID1)
#define bfin_write_CAN0_MB17_ID1(val)  bfin_write16(CAN0_MB17_ID1, val)
#define pCAN0_MB18_DATA0               ((uint16_t volatile *)CAN0_MB18_DATA0) /* CAN Controller 0 Mailbox 18 Data 0 Register */
#define bfin_read_CAN0_MB18_DATA0()    bfin_read16(CAN0_MB18_DATA0)
#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
#define pCAN0_MB18_DATA1               ((uint16_t volatile *)CAN0_MB18_DATA1) /* CAN Controller 0 Mailbox 18 Data 1 Register */
#define bfin_read_CAN0_MB18_DATA1()    bfin_read16(CAN0_MB18_DATA1)
#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
#define pCAN0_MB18_DATA2               ((uint16_t volatile *)CAN0_MB18_DATA2) /* CAN Controller 0 Mailbox 18 Data 2 Register */
#define bfin_read_CAN0_MB18_DATA2()    bfin_read16(CAN0_MB18_DATA2)
#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
#define pCAN0_MB18_DATA3               ((uint16_t volatile *)CAN0_MB18_DATA3) /* CAN Controller 0 Mailbox 18 Data 3 Register */
#define bfin_read_CAN0_MB18_DATA3()    bfin_read16(CAN0_MB18_DATA3)
#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
#define pCAN0_MB18_LENGTH              ((uint16_t volatile *)CAN0_MB18_LENGTH) /* CAN Controller 0 Mailbox 18 Length Register */
#define bfin_read_CAN0_MB18_LENGTH()   bfin_read16(CAN0_MB18_LENGTH)
#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
#define pCAN0_MB18_TIMESTAMP           ((uint16_t volatile *)CAN0_MB18_TIMESTAMP) /* CAN Controller 0 Mailbox 18 Timestamp Register */
#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
#define pCAN0_MB18_ID0                 ((uint16_t volatile *)CAN0_MB18_ID0) /* CAN Controller 0 Mailbox 18 ID0 Register */
#define bfin_read_CAN0_MB18_ID0()      bfin_read16(CAN0_MB18_ID0)
#define bfin_write_CAN0_MB18_ID0(val)  bfin_write16(CAN0_MB18_ID0, val)
#define pCAN0_MB18_ID1                 ((uint16_t volatile *)CAN0_MB18_ID1) /* CAN Controller 0 Mailbox 18 ID1 Register */
#define bfin_read_CAN0_MB18_ID1()      bfin_read16(CAN0_MB18_ID1)
#define bfin_write_CAN0_MB18_ID1(val)  bfin_write16(CAN0_MB18_ID1, val)
#define pCAN0_MB19_DATA0               ((uint16_t volatile *)CAN0_MB19_DATA0) /* CAN Controller 0 Mailbox 19 Data 0 Register */
#define bfin_read_CAN0_MB19_DATA0()    bfin_read16(CAN0_MB19_DATA0)
#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
#define pCAN0_MB19_DATA1               ((uint16_t volatile *)CAN0_MB19_DATA1) /* CAN Controller 0 Mailbox 19 Data 1 Register */
#define bfin_read_CAN0_MB19_DATA1()    bfin_read16(CAN0_MB19_DATA1)
#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
#define pCAN0_MB19_DATA2               ((uint16_t volatile *)CAN0_MB19_DATA2) /* CAN Controller 0 Mailbox 19 Data 2 Register */
#define bfin_read_CAN0_MB19_DATA2()    bfin_read16(CAN0_MB19_DATA2)
#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
#define pCAN0_MB19_DATA3               ((uint16_t volatile *)CAN0_MB19_DATA3) /* CAN Controller 0 Mailbox 19 Data 3 Register */
#define bfin_read_CAN0_MB19_DATA3()    bfin_read16(CAN0_MB19_DATA3)
#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
#define pCAN0_MB19_LENGTH              ((uint16_t volatile *)CAN0_MB19_LENGTH) /* CAN Controller 0 Mailbox 19 Length Register */
#define bfin_read_CAN0_MB19_LENGTH()   bfin_read16(CAN0_MB19_LENGTH)
#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
#define pCAN0_MB19_TIMESTAMP           ((uint16_t volatile *)CAN0_MB19_TIMESTAMP) /* CAN Controller 0 Mailbox 19 Timestamp Register */
#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
#define pCAN0_MB19_ID0                 ((uint16_t volatile *)CAN0_MB19_ID0) /* CAN Controller 0 Mailbox 19 ID0 Register */
#define bfin_read_CAN0_MB19_ID0()      bfin_read16(CAN0_MB19_ID0)
#define bfin_write_CAN0_MB19_ID0(val)  bfin_write16(CAN0_MB19_ID0, val)
#define pCAN0_MB19_ID1                 ((uint16_t volatile *)CAN0_MB19_ID1) /* CAN Controller 0 Mailbox 19 ID1 Register */
#define bfin_read_CAN0_MB19_ID1()      bfin_read16(CAN0_MB19_ID1)
#define bfin_write_CAN0_MB19_ID1(val)  bfin_write16(CAN0_MB19_ID1, val)
#define pCAN0_MB20_DATA0               ((uint16_t volatile *)CAN0_MB20_DATA0) /* CAN Controller 0 Mailbox 20 Data 0 Register */
#define bfin_read_CAN0_MB20_DATA0()    bfin_read16(CAN0_MB20_DATA0)
#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
#define pCAN0_MB20_DATA1               ((uint16_t volatile *)CAN0_MB20_DATA1) /* CAN Controller 0 Mailbox 20 Data 1 Register */
#define bfin_read_CAN0_MB20_DATA1()    bfin_read16(CAN0_MB20_DATA1)
#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
#define pCAN0_MB20_DATA2               ((uint16_t volatile *)CAN0_MB20_DATA2) /* CAN Controller 0 Mailbox 20 Data 2 Register */
#define bfin_read_CAN0_MB20_DATA2()    bfin_read16(CAN0_MB20_DATA2)
#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
#define pCAN0_MB20_DATA3               ((uint16_t volatile *)CAN0_MB20_DATA3) /* CAN Controller 0 Mailbox 20 Data 3 Register */
#define bfin_read_CAN0_MB20_DATA3()    bfin_read16(CAN0_MB20_DATA3)
#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
#define pCAN0_MB20_LENGTH              ((uint16_t volatile *)CAN0_MB20_LENGTH) /* CAN Controller 0 Mailbox 20 Length Register */
#define bfin_read_CAN0_MB20_LENGTH()   bfin_read16(CAN0_MB20_LENGTH)
#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
#define pCAN0_MB20_TIMESTAMP           ((uint16_t volatile *)CAN0_MB20_TIMESTAMP) /* CAN Controller 0 Mailbox 20 Timestamp Register */
#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
#define pCAN0_MB20_ID0                 ((uint16_t volatile *)CAN0_MB20_ID0) /* CAN Controller 0 Mailbox 20 ID0 Register */
#define bfin_read_CAN0_MB20_ID0()      bfin_read16(CAN0_MB20_ID0)
#define bfin_write_CAN0_MB20_ID0(val)  bfin_write16(CAN0_MB20_ID0, val)
#define pCAN0_MB20_ID1                 ((uint16_t volatile *)CAN0_MB20_ID1) /* CAN Controller 0 Mailbox 20 ID1 Register */
#define bfin_read_CAN0_MB20_ID1()      bfin_read16(CAN0_MB20_ID1)
#define bfin_write_CAN0_MB20_ID1(val)  bfin_write16(CAN0_MB20_ID1, val)
#define pCAN0_MB21_DATA0               ((uint16_t volatile *)CAN0_MB21_DATA0) /* CAN Controller 0 Mailbox 21 Data 0 Register */
#define bfin_read_CAN0_MB21_DATA0()    bfin_read16(CAN0_MB21_DATA0)
#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
#define pCAN0_MB21_DATA1               ((uint16_t volatile *)CAN0_MB21_DATA1) /* CAN Controller 0 Mailbox 21 Data 1 Register */
#define bfin_read_CAN0_MB21_DATA1()    bfin_read16(CAN0_MB21_DATA1)
#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
#define pCAN0_MB21_DATA2               ((uint16_t volatile *)CAN0_MB21_DATA2) /* CAN Controller 0 Mailbox 21 Data 2 Register */
#define bfin_read_CAN0_MB21_DATA2()    bfin_read16(CAN0_MB21_DATA2)
#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
#define pCAN0_MB21_DATA3               ((uint16_t volatile *)CAN0_MB21_DATA3) /* CAN Controller 0 Mailbox 21 Data 3 Register */
#define bfin_read_CAN0_MB21_DATA3()    bfin_read16(CAN0_MB21_DATA3)
#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
#define pCAN0_MB21_LENGTH              ((uint16_t volatile *)CAN0_MB21_LENGTH) /* CAN Controller 0 Mailbox 21 Length Register */
#define bfin_read_CAN0_MB21_LENGTH()   bfin_read16(CAN0_MB21_LENGTH)
#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
#define pCAN0_MB21_TIMESTAMP           ((uint16_t volatile *)CAN0_MB21_TIMESTAMP) /* CAN Controller 0 Mailbox 21 Timestamp Register */
#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
#define pCAN0_MB21_ID0                 ((uint16_t volatile *)CAN0_MB21_ID0) /* CAN Controller 0 Mailbox 21 ID0 Register */
#define bfin_read_CAN0_MB21_ID0()      bfin_read16(CAN0_MB21_ID0)
#define bfin_write_CAN0_MB21_ID0(val)  bfin_write16(CAN0_MB21_ID0, val)
#define pCAN0_MB21_ID1                 ((uint16_t volatile *)CAN0_MB21_ID1) /* CAN Controller 0 Mailbox 21 ID1 Register */
#define bfin_read_CAN0_MB21_ID1()      bfin_read16(CAN0_MB21_ID1)
#define bfin_write_CAN0_MB21_ID1(val)  bfin_write16(CAN0_MB21_ID1, val)
#define pCAN0_MB22_DATA0               ((uint16_t volatile *)CAN0_MB22_DATA0) /* CAN Controller 0 Mailbox 22 Data 0 Register */
#define bfin_read_CAN0_MB22_DATA0()    bfin_read16(CAN0_MB22_DATA0)
#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
#define pCAN0_MB22_DATA1               ((uint16_t volatile *)CAN0_MB22_DATA1) /* CAN Controller 0 Mailbox 22 Data 1 Register */
#define bfin_read_CAN0_MB22_DATA1()    bfin_read16(CAN0_MB22_DATA1)
#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
#define pCAN0_MB22_DATA2               ((uint16_t volatile *)CAN0_MB22_DATA2) /* CAN Controller 0 Mailbox 22 Data 2 Register */
#define bfin_read_CAN0_MB22_DATA2()    bfin_read16(CAN0_MB22_DATA2)
#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
#define pCAN0_MB22_DATA3               ((uint16_t volatile *)CAN0_MB22_DATA3) /* CAN Controller 0 Mailbox 22 Data 3 Register */
#define bfin_read_CAN0_MB22_DATA3()    bfin_read16(CAN0_MB22_DATA3)
#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
#define pCAN0_MB22_LENGTH              ((uint16_t volatile *)CAN0_MB22_LENGTH) /* CAN Controller 0 Mailbox 22 Length Register */
#define bfin_read_CAN0_MB22_LENGTH()   bfin_read16(CAN0_MB22_LENGTH)
#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
#define pCAN0_MB22_TIMESTAMP           ((uint16_t volatile *)CAN0_MB22_TIMESTAMP) /* CAN Controller 0 Mailbox 22 Timestamp Register */
#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
#define pCAN0_MB22_ID0                 ((uint16_t volatile *)CAN0_MB22_ID0) /* CAN Controller 0 Mailbox 22 ID0 Register */
#define bfin_read_CAN0_MB22_ID0()      bfin_read16(CAN0_MB22_ID0)
#define bfin_write_CAN0_MB22_ID0(val)  bfin_write16(CAN0_MB22_ID0, val)
#define pCAN0_MB22_ID1                 ((uint16_t volatile *)CAN0_MB22_ID1) /* CAN Controller 0 Mailbox 22 ID1 Register */
#define bfin_read_CAN0_MB22_ID1()      bfin_read16(CAN0_MB22_ID1)
#define bfin_write_CAN0_MB22_ID1(val)  bfin_write16(CAN0_MB22_ID1, val)
#define pCAN0_MB23_DATA0               ((uint16_t volatile *)CAN0_MB23_DATA0) /* CAN Controller 0 Mailbox 23 Data 0 Register */
#define bfin_read_CAN0_MB23_DATA0()    bfin_read16(CAN0_MB23_DATA0)
#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
#define pCAN0_MB23_DATA1               ((uint16_t volatile *)CAN0_MB23_DATA1) /* CAN Controller 0 Mailbox 23 Data 1 Register */
#define bfin_read_CAN0_MB23_DATA1()    bfin_read16(CAN0_MB23_DATA1)
#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
#define pCAN0_MB23_DATA2               ((uint16_t volatile *)CAN0_MB23_DATA2) /* CAN Controller 0 Mailbox 23 Data 2 Register */
#define bfin_read_CAN0_MB23_DATA2()    bfin_read16(CAN0_MB23_DATA2)
#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
#define pCAN0_MB23_DATA3               ((uint16_t volatile *)CAN0_MB23_DATA3) /* CAN Controller 0 Mailbox 23 Data 3 Register */
#define bfin_read_CAN0_MB23_DATA3()    bfin_read16(CAN0_MB23_DATA3)
#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
#define pCAN0_MB23_LENGTH              ((uint16_t volatile *)CAN0_MB23_LENGTH) /* CAN Controller 0 Mailbox 23 Length Register */
#define bfin_read_CAN0_MB23_LENGTH()   bfin_read16(CAN0_MB23_LENGTH)
#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
#define pCAN0_MB23_TIMESTAMP           ((uint16_t volatile *)CAN0_MB23_TIMESTAMP) /* CAN Controller 0 Mailbox 23 Timestamp Register */
#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
#define pCAN0_MB23_ID0                 ((uint16_t volatile *)CAN0_MB23_ID0) /* CAN Controller 0 Mailbox 23 ID0 Register */
#define bfin_read_CAN0_MB23_ID0()      bfin_read16(CAN0_MB23_ID0)
#define bfin_write_CAN0_MB23_ID0(val)  bfin_write16(CAN0_MB23_ID0, val)
#define pCAN0_MB23_ID1                 ((uint16_t volatile *)CAN0_MB23_ID1) /* CAN Controller 0 Mailbox 23 ID1 Register */
#define bfin_read_CAN0_MB23_ID1()      bfin_read16(CAN0_MB23_ID1)
#define bfin_write_CAN0_MB23_ID1(val)  bfin_write16(CAN0_MB23_ID1, val)
#define pCAN0_MB24_DATA0               ((uint16_t volatile *)CAN0_MB24_DATA0) /* CAN Controller 0 Mailbox 24 Data 0 Register */
#define bfin_read_CAN0_MB24_DATA0()    bfin_read16(CAN0_MB24_DATA0)
#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
#define pCAN0_MB24_DATA1               ((uint16_t volatile *)CAN0_MB24_DATA1) /* CAN Controller 0 Mailbox 24 Data 1 Register */
#define bfin_read_CAN0_MB24_DATA1()    bfin_read16(CAN0_MB24_DATA1)
#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
#define pCAN0_MB24_DATA2               ((uint16_t volatile *)CAN0_MB24_DATA2) /* CAN Controller 0 Mailbox 24 Data 2 Register */
#define bfin_read_CAN0_MB24_DATA2()    bfin_read16(CAN0_MB24_DATA2)
#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
#define pCAN0_MB24_DATA3               ((uint16_t volatile *)CAN0_MB24_DATA3) /* CAN Controller 0 Mailbox 24 Data 3 Register */
#define bfin_read_CAN0_MB24_DATA3()    bfin_read16(CAN0_MB24_DATA3)
#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
#define pCAN0_MB24_LENGTH              ((uint16_t volatile *)CAN0_MB24_LENGTH) /* CAN Controller 0 Mailbox 24 Length Register */
#define bfin_read_CAN0_MB24_LENGTH()   bfin_read16(CAN0_MB24_LENGTH)
#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
#define pCAN0_MB24_TIMESTAMP           ((uint16_t volatile *)CAN0_MB24_TIMESTAMP) /* CAN Controller 0 Mailbox 24 Timestamp Register */
#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
#define pCAN0_MB24_ID0                 ((uint16_t volatile *)CAN0_MB24_ID0) /* CAN Controller 0 Mailbox 24 ID0 Register */
#define bfin_read_CAN0_MB24_ID0()      bfin_read16(CAN0_MB24_ID0)
#define bfin_write_CAN0_MB24_ID0(val)  bfin_write16(CAN0_MB24_ID0, val)
#define pCAN0_MB24_ID1                 ((uint16_t volatile *)CAN0_MB24_ID1) /* CAN Controller 0 Mailbox 24 ID1 Register */
#define bfin_read_CAN0_MB24_ID1()      bfin_read16(CAN0_MB24_ID1)
#define bfin_write_CAN0_MB24_ID1(val)  bfin_write16(CAN0_MB24_ID1, val)
#define pCAN0_MB25_DATA0               ((uint16_t volatile *)CAN0_MB25_DATA0) /* CAN Controller 0 Mailbox 25 Data 0 Register */
#define bfin_read_CAN0_MB25_DATA0()    bfin_read16(CAN0_MB25_DATA0)
#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
#define pCAN0_MB25_DATA1               ((uint16_t volatile *)CAN0_MB25_DATA1) /* CAN Controller 0 Mailbox 25 Data 1 Register */
#define bfin_read_CAN0_MB25_DATA1()    bfin_read16(CAN0_MB25_DATA1)
#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
#define pCAN0_MB25_DATA2               ((uint16_t volatile *)CAN0_MB25_DATA2) /* CAN Controller 0 Mailbox 25 Data 2 Register */
#define bfin_read_CAN0_MB25_DATA2()    bfin_read16(CAN0_MB25_DATA2)
#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
#define pCAN0_MB25_DATA3               ((uint16_t volatile *)CAN0_MB25_DATA3) /* CAN Controller 0 Mailbox 25 Data 3 Register */
#define bfin_read_CAN0_MB25_DATA3()    bfin_read16(CAN0_MB25_DATA3)
#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
#define pCAN0_MB25_LENGTH              ((uint16_t volatile *)CAN0_MB25_LENGTH) /* CAN Controller 0 Mailbox 25 Length Register */
#define bfin_read_CAN0_MB25_LENGTH()   bfin_read16(CAN0_MB25_LENGTH)
#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
#define pCAN0_MB25_TIMESTAMP           ((uint16_t volatile *)CAN0_MB25_TIMESTAMP) /* CAN Controller 0 Mailbox 25 Timestamp Register */
#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
#define pCAN0_MB25_ID0                 ((uint16_t volatile *)CAN0_MB25_ID0) /* CAN Controller 0 Mailbox 25 ID0 Register */
#define bfin_read_CAN0_MB25_ID0()      bfin_read16(CAN0_MB25_ID0)
#define bfin_write_CAN0_MB25_ID0(val)  bfin_write16(CAN0_MB25_ID0, val)
#define pCAN0_MB25_ID1                 ((uint16_t volatile *)CAN0_MB25_ID1) /* CAN Controller 0 Mailbox 25 ID1 Register */
#define bfin_read_CAN0_MB25_ID1()      bfin_read16(CAN0_MB25_ID1)
#define bfin_write_CAN0_MB25_ID1(val)  bfin_write16(CAN0_MB25_ID1, val)
#define pCAN0_MB26_DATA0               ((uint16_t volatile *)CAN0_MB26_DATA0) /* CAN Controller 0 Mailbox 26 Data 0 Register */
#define bfin_read_CAN0_MB26_DATA0()    bfin_read16(CAN0_MB26_DATA0)
#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
#define pCAN0_MB26_DATA1               ((uint16_t volatile *)CAN0_MB26_DATA1) /* CAN Controller 0 Mailbox 26 Data 1 Register */
#define bfin_read_CAN0_MB26_DATA1()    bfin_read16(CAN0_MB26_DATA1)
#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
#define pCAN0_MB26_DATA2               ((uint16_t volatile *)CAN0_MB26_DATA2) /* CAN Controller 0 Mailbox 26 Data 2 Register */
#define bfin_read_CAN0_MB26_DATA2()    bfin_read16(CAN0_MB26_DATA2)
#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
#define pCAN0_MB26_DATA3               ((uint16_t volatile *)CAN0_MB26_DATA3) /* CAN Controller 0 Mailbox 26 Data 3 Register */
#define bfin_read_CAN0_MB26_DATA3()    bfin_read16(CAN0_MB26_DATA3)
#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
#define pCAN0_MB26_LENGTH              ((uint16_t volatile *)CAN0_MB26_LENGTH) /* CAN Controller 0 Mailbox 26 Length Register */
#define bfin_read_CAN0_MB26_LENGTH()   bfin_read16(CAN0_MB26_LENGTH)
#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
#define pCAN0_MB26_TIMESTAMP           ((uint16_t volatile *)CAN0_MB26_TIMESTAMP) /* CAN Controller 0 Mailbox 26 Timestamp Register */
#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
#define pCAN0_MB26_ID0                 ((uint16_t volatile *)CAN0_MB26_ID0) /* CAN Controller 0 Mailbox 26 ID0 Register */
#define bfin_read_CAN0_MB26_ID0()      bfin_read16(CAN0_MB26_ID0)
#define bfin_write_CAN0_MB26_ID0(val)  bfin_write16(CAN0_MB26_ID0, val)
#define pCAN0_MB26_ID1                 ((uint16_t volatile *)CAN0_MB26_ID1) /* CAN Controller 0 Mailbox 26 ID1 Register */
#define bfin_read_CAN0_MB26_ID1()      bfin_read16(CAN0_MB26_ID1)
#define bfin_write_CAN0_MB26_ID1(val)  bfin_write16(CAN0_MB26_ID1, val)
#define pCAN0_MB27_DATA0               ((uint16_t volatile *)CAN0_MB27_DATA0) /* CAN Controller 0 Mailbox 27 Data 0 Register */
#define bfin_read_CAN0_MB27_DATA0()    bfin_read16(CAN0_MB27_DATA0)
#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
#define pCAN0_MB27_DATA1               ((uint16_t volatile *)CAN0_MB27_DATA1) /* CAN Controller 0 Mailbox 27 Data 1 Register */
#define bfin_read_CAN0_MB27_DATA1()    bfin_read16(CAN0_MB27_DATA1)
#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
#define pCAN0_MB27_DATA2               ((uint16_t volatile *)CAN0_MB27_DATA2) /* CAN Controller 0 Mailbox 27 Data 2 Register */
#define bfin_read_CAN0_MB27_DATA2()    bfin_read16(CAN0_MB27_DATA2)
#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
#define pCAN0_MB27_DATA3               ((uint16_t volatile *)CAN0_MB27_DATA3) /* CAN Controller 0 Mailbox 27 Data 3 Register */
#define bfin_read_CAN0_MB27_DATA3()    bfin_read16(CAN0_MB27_DATA3)
#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
#define pCAN0_MB27_LENGTH              ((uint16_t volatile *)CAN0_MB27_LENGTH) /* CAN Controller 0 Mailbox 27 Length Register */
#define bfin_read_CAN0_MB27_LENGTH()   bfin_read16(CAN0_MB27_LENGTH)
#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
#define pCAN0_MB27_TIMESTAMP           ((uint16_t volatile *)CAN0_MB27_TIMESTAMP) /* CAN Controller 0 Mailbox 27 Timestamp Register */
#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
#define pCAN0_MB27_ID0                 ((uint16_t volatile *)CAN0_MB27_ID0) /* CAN Controller 0 Mailbox 27 ID0 Register */
#define bfin_read_CAN0_MB27_ID0()      bfin_read16(CAN0_MB27_ID0)
#define bfin_write_CAN0_MB27_ID0(val)  bfin_write16(CAN0_MB27_ID0, val)
#define pCAN0_MB27_ID1                 ((uint16_t volatile *)CAN0_MB27_ID1) /* CAN Controller 0 Mailbox 27 ID1 Register */
#define bfin_read_CAN0_MB27_ID1()      bfin_read16(CAN0_MB27_ID1)
#define bfin_write_CAN0_MB27_ID1(val)  bfin_write16(CAN0_MB27_ID1, val)
#define pCAN0_MB28_DATA0               ((uint16_t volatile *)CAN0_MB28_DATA0) /* CAN Controller 0 Mailbox 28 Data 0 Register */
#define bfin_read_CAN0_MB28_DATA0()    bfin_read16(CAN0_MB28_DATA0)
#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
#define pCAN0_MB28_DATA1               ((uint16_t volatile *)CAN0_MB28_DATA1) /* CAN Controller 0 Mailbox 28 Data 1 Register */
#define bfin_read_CAN0_MB28_DATA1()    bfin_read16(CAN0_MB28_DATA1)
#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
#define pCAN0_MB28_DATA2               ((uint16_t volatile *)CAN0_MB28_DATA2) /* CAN Controller 0 Mailbox 28 Data 2 Register */
#define bfin_read_CAN0_MB28_DATA2()    bfin_read16(CAN0_MB28_DATA2)
#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
#define pCAN0_MB28_DATA3               ((uint16_t volatile *)CAN0_MB28_DATA3) /* CAN Controller 0 Mailbox 28 Data 3 Register */
#define bfin_read_CAN0_MB28_DATA3()    bfin_read16(CAN0_MB28_DATA3)
#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
#define pCAN0_MB28_LENGTH              ((uint16_t volatile *)CAN0_MB28_LENGTH) /* CAN Controller 0 Mailbox 28 Length Register */
#define bfin_read_CAN0_MB28_LENGTH()   bfin_read16(CAN0_MB28_LENGTH)
#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
#define pCAN0_MB28_TIMESTAMP           ((uint16_t volatile *)CAN0_MB28_TIMESTAMP) /* CAN Controller 0 Mailbox 28 Timestamp Register */
#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
#define pCAN0_MB28_ID0                 ((uint16_t volatile *)CAN0_MB28_ID0) /* CAN Controller 0 Mailbox 28 ID0 Register */
#define bfin_read_CAN0_MB28_ID0()      bfin_read16(CAN0_MB28_ID0)
#define bfin_write_CAN0_MB28_ID0(val)  bfin_write16(CAN0_MB28_ID0, val)
#define pCAN0_MB28_ID1                 ((uint16_t volatile *)CAN0_MB28_ID1) /* CAN Controller 0 Mailbox 28 ID1 Register */
#define bfin_read_CAN0_MB28_ID1()      bfin_read16(CAN0_MB28_ID1)
#define bfin_write_CAN0_MB28_ID1(val)  bfin_write16(CAN0_MB28_ID1, val)
#define pCAN0_MB29_DATA0               ((uint16_t volatile *)CAN0_MB29_DATA0) /* CAN Controller 0 Mailbox 29 Data 0 Register */
#define bfin_read_CAN0_MB29_DATA0()    bfin_read16(CAN0_MB29_DATA0)
#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
#define pCAN0_MB29_DATA1               ((uint16_t volatile *)CAN0_MB29_DATA1) /* CAN Controller 0 Mailbox 29 Data 1 Register */
#define bfin_read_CAN0_MB29_DATA1()    bfin_read16(CAN0_MB29_DATA1)
#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
#define pCAN0_MB29_DATA2               ((uint16_t volatile *)CAN0_MB29_DATA2) /* CAN Controller 0 Mailbox 29 Data 2 Register */
#define bfin_read_CAN0_MB29_DATA2()    bfin_read16(CAN0_MB29_DATA2)
#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
#define pCAN0_MB29_DATA3               ((uint16_t volatile *)CAN0_MB29_DATA3) /* CAN Controller 0 Mailbox 29 Data 3 Register */
#define bfin_read_CAN0_MB29_DATA3()    bfin_read16(CAN0_MB29_DATA3)
#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
#define pCAN0_MB29_LENGTH              ((uint16_t volatile *)CAN0_MB29_LENGTH) /* CAN Controller 0 Mailbox 29 Length Register */
#define bfin_read_CAN0_MB29_LENGTH()   bfin_read16(CAN0_MB29_LENGTH)
#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
#define pCAN0_MB29_TIMESTAMP           ((uint16_t volatile *)CAN0_MB29_TIMESTAMP) /* CAN Controller 0 Mailbox 29 Timestamp Register */
#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
#define pCAN0_MB29_ID0                 ((uint16_t volatile *)CAN0_MB29_ID0) /* CAN Controller 0 Mailbox 29 ID0 Register */
#define bfin_read_CAN0_MB29_ID0()      bfin_read16(CAN0_MB29_ID0)
#define bfin_write_CAN0_MB29_ID0(val)  bfin_write16(CAN0_MB29_ID0, val)
#define pCAN0_MB29_ID1                 ((uint16_t volatile *)CAN0_MB29_ID1) /* CAN Controller 0 Mailbox 29 ID1 Register */
#define bfin_read_CAN0_MB29_ID1()      bfin_read16(CAN0_MB29_ID1)
#define bfin_write_CAN0_MB29_ID1(val)  bfin_write16(CAN0_MB29_ID1, val)
#define pCAN0_MB30_DATA0               ((uint16_t volatile *)CAN0_MB30_DATA0) /* CAN Controller 0 Mailbox 30 Data 0 Register */
#define bfin_read_CAN0_MB30_DATA0()    bfin_read16(CAN0_MB30_DATA0)
#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
#define pCAN0_MB30_DATA1               ((uint16_t volatile *)CAN0_MB30_DATA1) /* CAN Controller 0 Mailbox 30 Data 1 Register */
#define bfin_read_CAN0_MB30_DATA1()    bfin_read16(CAN0_MB30_DATA1)
#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
#define pCAN0_MB30_DATA2               ((uint16_t volatile *)CAN0_MB30_DATA2) /* CAN Controller 0 Mailbox 30 Data 2 Register */
#define bfin_read_CAN0_MB30_DATA2()    bfin_read16(CAN0_MB30_DATA2)
#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
#define pCAN0_MB30_DATA3               ((uint16_t volatile *)CAN0_MB30_DATA3) /* CAN Controller 0 Mailbox 30 Data 3 Register */
#define bfin_read_CAN0_MB30_DATA3()    bfin_read16(CAN0_MB30_DATA3)
#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
#define pCAN0_MB30_LENGTH              ((uint16_t volatile *)CAN0_MB30_LENGTH) /* CAN Controller 0 Mailbox 30 Length Register */
#define bfin_read_CAN0_MB30_LENGTH()   bfin_read16(CAN0_MB30_LENGTH)
#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
#define pCAN0_MB30_TIMESTAMP           ((uint16_t volatile *)CAN0_MB30_TIMESTAMP) /* CAN Controller 0 Mailbox 30 Timestamp Register */
#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
#define pCAN0_MB30_ID0                 ((uint16_t volatile *)CAN0_MB30_ID0) /* CAN Controller 0 Mailbox 30 ID0 Register */
#define bfin_read_CAN0_MB30_ID0()      bfin_read16(CAN0_MB30_ID0)
#define bfin_write_CAN0_MB30_ID0(val)  bfin_write16(CAN0_MB30_ID0, val)
#define pCAN0_MB30_ID1                 ((uint16_t volatile *)CAN0_MB30_ID1) /* CAN Controller 0 Mailbox 30 ID1 Register */
#define bfin_read_CAN0_MB30_ID1()      bfin_read16(CAN0_MB30_ID1)
#define bfin_write_CAN0_MB30_ID1(val)  bfin_write16(CAN0_MB30_ID1, val)
#define pCAN0_MB31_DATA0               ((uint16_t volatile *)CAN0_MB31_DATA0) /* CAN Controller 0 Mailbox 31 Data 0 Register */
#define bfin_read_CAN0_MB31_DATA0()    bfin_read16(CAN0_MB31_DATA0)
#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
#define pCAN0_MB31_DATA1               ((uint16_t volatile *)CAN0_MB31_DATA1) /* CAN Controller 0 Mailbox 31 Data 1 Register */
#define bfin_read_CAN0_MB31_DATA1()    bfin_read16(CAN0_MB31_DATA1)
#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
#define pCAN0_MB31_DATA2               ((uint16_t volatile *)CAN0_MB31_DATA2) /* CAN Controller 0 Mailbox 31 Data 2 Register */
#define bfin_read_CAN0_MB31_DATA2()    bfin_read16(CAN0_MB31_DATA2)
#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
#define pCAN0_MB31_DATA3               ((uint16_t volatile *)CAN0_MB31_DATA3) /* CAN Controller 0 Mailbox 31 Data 3 Register */
#define bfin_read_CAN0_MB31_DATA3()    bfin_read16(CAN0_MB31_DATA3)
#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
#define pCAN0_MB31_LENGTH              ((uint16_t volatile *)CAN0_MB31_LENGTH) /* CAN Controller 0 Mailbox 31 Length Register */
#define bfin_read_CAN0_MB31_LENGTH()   bfin_read16(CAN0_MB31_LENGTH)
#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
#define pCAN0_MB31_TIMESTAMP           ((uint16_t volatile *)CAN0_MB31_TIMESTAMP) /* CAN Controller 0 Mailbox 31 Timestamp Register */
#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
#define pCAN0_MB31_ID0                 ((uint16_t volatile *)CAN0_MB31_ID0) /* CAN Controller 0 Mailbox 31 ID0 Register */
#define bfin_read_CAN0_MB31_ID0()      bfin_read16(CAN0_MB31_ID0)
#define bfin_write_CAN0_MB31_ID0(val)  bfin_write16(CAN0_MB31_ID0, val)
#define pCAN0_MB31_ID1                 ((uint16_t volatile *)CAN0_MB31_ID1) /* CAN Controller 0 Mailbox 31 ID1 Register */
#define bfin_read_CAN0_MB31_ID1()      bfin_read16(CAN0_MB31_ID1)
#define bfin_write_CAN0_MB31_ID1(val)  bfin_write16(CAN0_MB31_ID1, val)
#define pCAN1_MC1                      ((uint16_t volatile *)CAN1_MC1) /* CAN Controller 1 Mailbox Configuration Register 1 */
#define bfin_read_CAN1_MC1()           bfin_read16(CAN1_MC1)
#define bfin_write_CAN1_MC1(val)       bfin_write16(CAN1_MC1, val)
#define pCAN1_MD1                      ((uint16_t volatile *)CAN1_MD1) /* CAN Controller 1 Mailbox Direction Register 1 */
#define bfin_read_CAN1_MD1()           bfin_read16(CAN1_MD1)
#define bfin_write_CAN1_MD1(val)       bfin_write16(CAN1_MD1, val)
#define pCAN1_TRS1                     ((uint16_t volatile *)CAN1_TRS1) /* CAN Controller 1 Transmit Request Set Register 1 */
#define bfin_read_CAN1_TRS1()          bfin_read16(CAN1_TRS1)
#define bfin_write_CAN1_TRS1(val)      bfin_write16(CAN1_TRS1, val)
#define pCAN1_TRR1                     ((uint16_t volatile *)CAN1_TRR1) /* CAN Controller 1 Transmit Request Reset Register 1 */
#define bfin_read_CAN1_TRR1()          bfin_read16(CAN1_TRR1)
#define bfin_write_CAN1_TRR1(val)      bfin_write16(CAN1_TRR1, val)
#define pCAN1_TA1                      ((uint16_t volatile *)CAN1_TA1) /* CAN Controller 1 Transmit Acknowledge Register 1 */
#define bfin_read_CAN1_TA1()           bfin_read16(CAN1_TA1)
#define bfin_write_CAN1_TA1(val)       bfin_write16(CAN1_TA1, val)
#define pCAN1_AA1                      ((uint16_t volatile *)CAN1_AA1) /* CAN Controller 1 Abort Acknowledge Register 1 */
#define bfin_read_CAN1_AA1()           bfin_read16(CAN1_AA1)
#define bfin_write_CAN1_AA1(val)       bfin_write16(CAN1_AA1, val)
#define pCAN1_RMP1                     ((uint16_t volatile *)CAN1_RMP1) /* CAN Controller 1 Receive Message Pending Register 1 */
#define bfin_read_CAN1_RMP1()          bfin_read16(CAN1_RMP1)
#define bfin_write_CAN1_RMP1(val)      bfin_write16(CAN1_RMP1, val)
#define pCAN1_RML1                     ((uint16_t volatile *)CAN1_RML1) /* CAN Controller 1 Receive Message Lost Register 1 */
#define bfin_read_CAN1_RML1()          bfin_read16(CAN1_RML1)
#define bfin_write_CAN1_RML1(val)      bfin_write16(CAN1_RML1, val)
#define pCAN1_MBTIF1                   ((uint16_t volatile *)CAN1_MBTIF1) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBTIF1()        bfin_read16(CAN1_MBTIF1)
#define bfin_write_CAN1_MBTIF1(val)    bfin_write16(CAN1_MBTIF1, val)
#define pCAN1_MBRIF1                   ((uint16_t volatile *)CAN1_MBRIF1) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
#define bfin_read_CAN1_MBRIF1()        bfin_read16(CAN1_MBRIF1)
#define bfin_write_CAN1_MBRIF1(val)    bfin_write16(CAN1_MBRIF1, val)
#define pCAN1_MBIM1                    ((uint16_t volatile *)CAN1_MBIM1) /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
#define bfin_read_CAN1_MBIM1()         bfin_read16(CAN1_MBIM1)
#define bfin_write_CAN1_MBIM1(val)     bfin_write16(CAN1_MBIM1, val)
#define pCAN1_RFH1                     ((uint16_t volatile *)CAN1_RFH1) /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
#define bfin_read_CAN1_RFH1()          bfin_read16(CAN1_RFH1)
#define bfin_write_CAN1_RFH1(val)      bfin_write16(CAN1_RFH1, val)
#define pCAN1_OPSS1                    ((uint16_t volatile *)CAN1_OPSS1) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
#define bfin_read_CAN1_OPSS1()         bfin_read16(CAN1_OPSS1)
#define bfin_write_CAN1_OPSS1(val)     bfin_write16(CAN1_OPSS1, val)
#define pCAN1_MC2                      ((uint16_t volatile *)CAN1_MC2) /* CAN Controller 1 Mailbox Configuration Register 2 */
#define bfin_read_CAN1_MC2()           bfin_read16(CAN1_MC2)
#define bfin_write_CAN1_MC2(val)       bfin_write16(CAN1_MC2, val)
#define pCAN1_MD2                      ((uint16_t volatile *)CAN1_MD2) /* CAN Controller 1 Mailbox Direction Register 2 */
#define bfin_read_CAN1_MD2()           bfin_read16(CAN1_MD2)
#define bfin_write_CAN1_MD2(val)       bfin_write16(CAN1_MD2, val)
#define pCAN1_TRS2                     ((uint16_t volatile *)CAN1_TRS2) /* CAN Controller 1 Transmit Request Set Register 2 */
#define bfin_read_CAN1_TRS2()          bfin_read16(CAN1_TRS2)
#define bfin_write_CAN1_TRS2(val)      bfin_write16(CAN1_TRS2, val)
#define pCAN1_TRR2                     ((uint16_t volatile *)CAN1_TRR2) /* CAN Controller 1 Transmit Request Reset Register 2 */
#define bfin_read_CAN1_TRR2()          bfin_read16(CAN1_TRR2)
#define bfin_write_CAN1_TRR2(val)      bfin_write16(CAN1_TRR2, val)
#define pCAN1_TA2                      ((uint16_t volatile *)CAN1_TA2) /* CAN Controller 1 Transmit Acknowledge Register 2 */
#define bfin_read_CAN1_TA2()           bfin_read16(CAN1_TA2)
#define bfin_write_CAN1_TA2(val)       bfin_write16(CAN1_TA2, val)
#define pCAN1_AA2                      ((uint16_t volatile *)CAN1_AA2) /* CAN Controller 1 Abort Acknowledge Register 2 */
#define bfin_read_CAN1_AA2()           bfin_read16(CAN1_AA2)
#define bfin_write_CAN1_AA2(val)       bfin_write16(CAN1_AA2, val)
#define pCAN1_RMP2                     ((uint16_t volatile *)CAN1_RMP2) /* CAN Controller 1 Receive Message Pending Register 2 */
#define bfin_read_CAN1_RMP2()          bfin_read16(CAN1_RMP2)
#define bfin_write_CAN1_RMP2(val)      bfin_write16(CAN1_RMP2, val)
#define pCAN1_RML2                     ((uint16_t volatile *)CAN1_RML2) /* CAN Controller 1 Receive Message Lost Register 2 */
#define bfin_read_CAN1_RML2()          bfin_read16(CAN1_RML2)
#define bfin_write_CAN1_RML2(val)      bfin_write16(CAN1_RML2, val)
#define pCAN1_MBTIF2                   ((uint16_t volatile *)CAN1_MBTIF2) /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBTIF2()        bfin_read16(CAN1_MBTIF2)
#define bfin_write_CAN1_MBTIF2(val)    bfin_write16(CAN1_MBTIF2, val)
#define pCAN1_MBRIF2                   ((uint16_t volatile *)CAN1_MBRIF2) /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
#define bfin_read_CAN1_MBRIF2()        bfin_read16(CAN1_MBRIF2)
#define bfin_write_CAN1_MBRIF2(val)    bfin_write16(CAN1_MBRIF2, val)
#define pCAN1_MBIM2                    ((uint16_t volatile *)CAN1_MBIM2) /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
#define bfin_read_CAN1_MBIM2()         bfin_read16(CAN1_MBIM2)
#define bfin_write_CAN1_MBIM2(val)     bfin_write16(CAN1_MBIM2, val)
#define pCAN1_RFH2                     ((uint16_t volatile *)CAN1_RFH2) /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
#define bfin_read_CAN1_RFH2()          bfin_read16(CAN1_RFH2)
#define bfin_write_CAN1_RFH2(val)      bfin_write16(CAN1_RFH2, val)
#define pCAN1_OPSS2                    ((uint16_t volatile *)CAN1_OPSS2) /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
#define bfin_read_CAN1_OPSS2()         bfin_read16(CAN1_OPSS2)
#define bfin_write_CAN1_OPSS2(val)     bfin_write16(CAN1_OPSS2, val)
#define pCAN1_CLOCK                    ((uint16_t volatile *)CAN1_CLOCK) /* CAN Controller 1 Clock Register */
#define bfin_read_CAN1_CLOCK()         bfin_read16(CAN1_CLOCK)
#define bfin_write_CAN1_CLOCK(val)     bfin_write16(CAN1_CLOCK, val)
#define pCAN1_TIMING                   ((uint16_t volatile *)CAN1_TIMING) /* CAN Controller 1 Timing Register */
#define bfin_read_CAN1_TIMING()        bfin_read16(CAN1_TIMING)
#define bfin_write_CAN1_TIMING(val)    bfin_write16(CAN1_TIMING, val)
#define pCAN1_DEBUG                    ((uint16_t volatile *)CAN1_DEBUG) /* CAN Controller 1 Debug Register */
#define bfin_read_CAN1_DEBUG()         bfin_read16(CAN1_DEBUG)
#define bfin_write_CAN1_DEBUG(val)     bfin_write16(CAN1_DEBUG, val)
#define pCAN1_STATUS                   ((uint16_t volatile *)CAN1_STATUS) /* CAN Controller 1 Global Status Register */
#define bfin_read_CAN1_STATUS()        bfin_read16(CAN1_STATUS)
#define bfin_write_CAN1_STATUS(val)    bfin_write16(CAN1_STATUS, val)
#define pCAN1_CEC                      ((uint16_t volatile *)CAN1_CEC) /* CAN Controller 1 Error Counter Register */
#define bfin_read_CAN1_CEC()           bfin_read16(CAN1_CEC)
#define bfin_write_CAN1_CEC(val)       bfin_write16(CAN1_CEC, val)
#define pCAN1_GIS                      ((uint16_t volatile *)CAN1_GIS) /* CAN Controller 1 Global Interrupt Status Register */
#define bfin_read_CAN1_GIS()           bfin_read16(CAN1_GIS)
#define bfin_write_CAN1_GIS(val)       bfin_write16(CAN1_GIS, val)
#define pCAN1_GIM                      ((uint16_t volatile *)CAN1_GIM) /* CAN Controller 1 Global Interrupt Mask Register */
#define bfin_read_CAN1_GIM()           bfin_read16(CAN1_GIM)
#define bfin_write_CAN1_GIM(val)       bfin_write16(CAN1_GIM, val)
#define pCAN1_GIF                      ((uint16_t volatile *)CAN1_GIF) /* CAN Controller 1 Global Interrupt Flag Register */
#define bfin_read_CAN1_GIF()           bfin_read16(CAN1_GIF)
#define bfin_write_CAN1_GIF(val)       bfin_write16(CAN1_GIF, val)
#define pCAN1_CONTROL                  ((uint16_t volatile *)CAN1_CONTROL) /* CAN Controller 1 Master Control Register */
#define bfin_read_CAN1_CONTROL()       bfin_read16(CAN1_CONTROL)
#define bfin_write_CAN1_CONTROL(val)   bfin_write16(CAN1_CONTROL, val)
#define pCAN1_INTR                     ((uint16_t volatile *)CAN1_INTR) /* CAN Controller 1 Interrupt Pending Register */
#define bfin_read_CAN1_INTR()          bfin_read16(CAN1_INTR)
#define bfin_write_CAN1_INTR(val)      bfin_write16(CAN1_INTR, val)
#define pCAN1_MBTD                     ((uint16_t volatile *)CAN1_MBTD) /* CAN Controller 1 Mailbox Temporary Disable Register */
#define bfin_read_CAN1_MBTD()          bfin_read16(CAN1_MBTD)
#define bfin_write_CAN1_MBTD(val)      bfin_write16(CAN1_MBTD, val)
#define pCAN1_EWR                      ((uint16_t volatile *)CAN1_EWR) /* CAN Controller 1 Programmable Warning Level Register */
#define bfin_read_CAN1_EWR()           bfin_read16(CAN1_EWR)
#define bfin_write_CAN1_EWR(val)       bfin_write16(CAN1_EWR, val)
#define pCAN1_ESR                      ((uint16_t volatile *)CAN1_ESR) /* CAN Controller 1 Error Status Register */
#define bfin_read_CAN1_ESR()           bfin_read16(CAN1_ESR)
#define bfin_write_CAN1_ESR(val)       bfin_write16(CAN1_ESR, val)
#define pCAN1_UCCNT                    ((uint16_t volatile *)CAN1_UCCNT) /* CAN Controller 1 Universal Counter Register */
#define bfin_read_CAN1_UCCNT()         bfin_read16(CAN1_UCCNT)
#define bfin_write_CAN1_UCCNT(val)     bfin_write16(CAN1_UCCNT, val)
#define pCAN1_UCRC                     ((uint16_t volatile *)CAN1_UCRC) /* CAN Controller 1 Universal Counter Force Reload Register */
#define bfin_read_CAN1_UCRC()          bfin_read16(CAN1_UCRC)
#define bfin_write_CAN1_UCRC(val)      bfin_write16(CAN1_UCRC, val)
#define pCAN1_UCCNF                    ((uint16_t volatile *)CAN1_UCCNF) /* CAN Controller 1 Universal Counter Configuration Register */
#define bfin_read_CAN1_UCCNF()         bfin_read16(CAN1_UCCNF)
#define bfin_write_CAN1_UCCNF(val)     bfin_write16(CAN1_UCCNF, val)
#define pCAN1_AM00L                    ((uint16_t volatile *)CAN1_AM00L) /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
#define bfin_read_CAN1_AM00L()         bfin_read16(CAN1_AM00L)
#define bfin_write_CAN1_AM00L(val)     bfin_write16(CAN1_AM00L, val)
#define pCAN1_AM00H                    ((uint16_t volatile *)CAN1_AM00H) /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM00H()         bfin_read16(CAN1_AM00H)
#define bfin_write_CAN1_AM00H(val)     bfin_write16(CAN1_AM00H, val)
#define pCAN1_AM01L                    ((uint16_t volatile *)CAN1_AM01L) /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
#define bfin_read_CAN1_AM01L()         bfin_read16(CAN1_AM01L)
#define bfin_write_CAN1_AM01L(val)     bfin_write16(CAN1_AM01L, val)
#define pCAN1_AM01H                    ((uint16_t volatile *)CAN1_AM01H) /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM01H()         bfin_read16(CAN1_AM01H)
#define bfin_write_CAN1_AM01H(val)     bfin_write16(CAN1_AM01H, val)
#define pCAN1_AM02L                    ((uint16_t volatile *)CAN1_AM02L) /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
#define bfin_read_CAN1_AM02L()         bfin_read16(CAN1_AM02L)
#define bfin_write_CAN1_AM02L(val)     bfin_write16(CAN1_AM02L, val)
#define pCAN1_AM02H                    ((uint16_t volatile *)CAN1_AM02H) /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM02H()         bfin_read16(CAN1_AM02H)
#define bfin_write_CAN1_AM02H(val)     bfin_write16(CAN1_AM02H, val)
#define pCAN1_AM03L                    ((uint16_t volatile *)CAN1_AM03L) /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
#define bfin_read_CAN1_AM03L()         bfin_read16(CAN1_AM03L)
#define bfin_write_CAN1_AM03L(val)     bfin_write16(CAN1_AM03L, val)
#define pCAN1_AM03H                    ((uint16_t volatile *)CAN1_AM03H) /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM03H()         bfin_read16(CAN1_AM03H)
#define bfin_write_CAN1_AM03H(val)     bfin_write16(CAN1_AM03H, val)
#define pCAN1_AM04L                    ((uint16_t volatile *)CAN1_AM04L) /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
#define bfin_read_CAN1_AM04L()         bfin_read16(CAN1_AM04L)
#define bfin_write_CAN1_AM04L(val)     bfin_write16(CAN1_AM04L, val)
#define pCAN1_AM04H                    ((uint16_t volatile *)CAN1_AM04H) /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM04H()         bfin_read16(CAN1_AM04H)
#define bfin_write_CAN1_AM04H(val)     bfin_write16(CAN1_AM04H, val)
#define pCAN1_AM05L                    ((uint16_t volatile *)CAN1_AM05L) /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
#define bfin_read_CAN1_AM05L()         bfin_read16(CAN1_AM05L)
#define bfin_write_CAN1_AM05L(val)     bfin_write16(CAN1_AM05L, val)
#define pCAN1_AM05H                    ((uint16_t volatile *)CAN1_AM05H) /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM05H()         bfin_read16(CAN1_AM05H)
#define bfin_write_CAN1_AM05H(val)     bfin_write16(CAN1_AM05H, val)
#define pCAN1_AM06L                    ((uint16_t volatile *)CAN1_AM06L) /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
#define bfin_read_CAN1_AM06L()         bfin_read16(CAN1_AM06L)
#define bfin_write_CAN1_AM06L(val)     bfin_write16(CAN1_AM06L, val)
#define pCAN1_AM06H                    ((uint16_t volatile *)CAN1_AM06H) /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM06H()         bfin_read16(CAN1_AM06H)
#define bfin_write_CAN1_AM06H(val)     bfin_write16(CAN1_AM06H, val)
#define pCAN1_AM07L                    ((uint16_t volatile *)CAN1_AM07L) /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
#define bfin_read_CAN1_AM07L()         bfin_read16(CAN1_AM07L)
#define bfin_write_CAN1_AM07L(val)     bfin_write16(CAN1_AM07L, val)
#define pCAN1_AM07H                    ((uint16_t volatile *)CAN1_AM07H) /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM07H()         bfin_read16(CAN1_AM07H)
#define bfin_write_CAN1_AM07H(val)     bfin_write16(CAN1_AM07H, val)
#define pCAN1_AM08L                    ((uint16_t volatile *)CAN1_AM08L) /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
#define bfin_read_CAN1_AM08L()         bfin_read16(CAN1_AM08L)
#define bfin_write_CAN1_AM08L(val)     bfin_write16(CAN1_AM08L, val)
#define pCAN1_AM08H                    ((uint16_t volatile *)CAN1_AM08H) /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM08H()         bfin_read16(CAN1_AM08H)
#define bfin_write_CAN1_AM08H(val)     bfin_write16(CAN1_AM08H, val)
#define pCAN1_AM09L                    ((uint16_t volatile *)CAN1_AM09L) /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
#define bfin_read_CAN1_AM09L()         bfin_read16(CAN1_AM09L)
#define bfin_write_CAN1_AM09L(val)     bfin_write16(CAN1_AM09L, val)
#define pCAN1_AM09H                    ((uint16_t volatile *)CAN1_AM09H) /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM09H()         bfin_read16(CAN1_AM09H)
#define bfin_write_CAN1_AM09H(val)     bfin_write16(CAN1_AM09H, val)
#define pCAN1_AM10L                    ((uint16_t volatile *)CAN1_AM10L) /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
#define bfin_read_CAN1_AM10L()         bfin_read16(CAN1_AM10L)
#define bfin_write_CAN1_AM10L(val)     bfin_write16(CAN1_AM10L, val)
#define pCAN1_AM10H                    ((uint16_t volatile *)CAN1_AM10H) /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM10H()         bfin_read16(CAN1_AM10H)
#define bfin_write_CAN1_AM10H(val)     bfin_write16(CAN1_AM10H, val)
#define pCAN1_AM11L                    ((uint16_t volatile *)CAN1_AM11L) /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
#define bfin_read_CAN1_AM11L()         bfin_read16(CAN1_AM11L)
#define bfin_write_CAN1_AM11L(val)     bfin_write16(CAN1_AM11L, val)
#define pCAN1_AM11H                    ((uint16_t volatile *)CAN1_AM11H) /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM11H()         bfin_read16(CAN1_AM11H)
#define bfin_write_CAN1_AM11H(val)     bfin_write16(CAN1_AM11H, val)
#define pCAN1_AM12L                    ((uint16_t volatile *)CAN1_AM12L) /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
#define bfin_read_CAN1_AM12L()         bfin_read16(CAN1_AM12L)
#define bfin_write_CAN1_AM12L(val)     bfin_write16(CAN1_AM12L, val)
#define pCAN1_AM12H                    ((uint16_t volatile *)CAN1_AM12H) /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM12H()         bfin_read16(CAN1_AM12H)
#define bfin_write_CAN1_AM12H(val)     bfin_write16(CAN1_AM12H, val)
#define pCAN1_AM13L                    ((uint16_t volatile *)CAN1_AM13L) /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
#define bfin_read_CAN1_AM13L()         bfin_read16(CAN1_AM13L)
#define bfin_write_CAN1_AM13L(val)     bfin_write16(CAN1_AM13L, val)
#define pCAN1_AM13H                    ((uint16_t volatile *)CAN1_AM13H) /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM13H()         bfin_read16(CAN1_AM13H)
#define bfin_write_CAN1_AM13H(val)     bfin_write16(CAN1_AM13H, val)
#define pCAN1_AM14L                    ((uint16_t volatile *)CAN1_AM14L) /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
#define bfin_read_CAN1_AM14L()         bfin_read16(CAN1_AM14L)
#define bfin_write_CAN1_AM14L(val)     bfin_write16(CAN1_AM14L, val)
#define pCAN1_AM14H                    ((uint16_t volatile *)CAN1_AM14H) /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM14H()         bfin_read16(CAN1_AM14H)
#define bfin_write_CAN1_AM14H(val)     bfin_write16(CAN1_AM14H, val)
#define pCAN1_AM15L                    ((uint16_t volatile *)CAN1_AM15L) /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
#define bfin_read_CAN1_AM15L()         bfin_read16(CAN1_AM15L)
#define bfin_write_CAN1_AM15L(val)     bfin_write16(CAN1_AM15L, val)
#define pCAN1_AM15H                    ((uint16_t volatile *)CAN1_AM15H) /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM15H()         bfin_read16(CAN1_AM15H)
#define bfin_write_CAN1_AM15H(val)     bfin_write16(CAN1_AM15H, val)
#define pCAN1_AM16L                    ((uint16_t volatile *)CAN1_AM16L) /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
#define bfin_read_CAN1_AM16L()         bfin_read16(CAN1_AM16L)
#define bfin_write_CAN1_AM16L(val)     bfin_write16(CAN1_AM16L, val)
#define pCAN1_AM16H                    ((uint16_t volatile *)CAN1_AM16H) /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM16H()         bfin_read16(CAN1_AM16H)
#define bfin_write_CAN1_AM16H(val)     bfin_write16(CAN1_AM16H, val)
#define pCAN1_AM17L                    ((uint16_t volatile *)CAN1_AM17L) /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
#define bfin_read_CAN1_AM17L()         bfin_read16(CAN1_AM17L)
#define bfin_write_CAN1_AM17L(val)     bfin_write16(CAN1_AM17L, val)
#define pCAN1_AM17H                    ((uint16_t volatile *)CAN1_AM17H) /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM17H()         bfin_read16(CAN1_AM17H)
#define bfin_write_CAN1_AM17H(val)     bfin_write16(CAN1_AM17H, val)
#define pCAN1_AM18L                    ((uint16_t volatile *)CAN1_AM18L) /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
#define bfin_read_CAN1_AM18L()         bfin_read16(CAN1_AM18L)
#define bfin_write_CAN1_AM18L(val)     bfin_write16(CAN1_AM18L, val)
#define pCAN1_AM18H                    ((uint16_t volatile *)CAN1_AM18H) /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM18H()         bfin_read16(CAN1_AM18H)
#define bfin_write_CAN1_AM18H(val)     bfin_write16(CAN1_AM18H, val)
#define pCAN1_AM19L                    ((uint16_t volatile *)CAN1_AM19L) /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
#define bfin_read_CAN1_AM19L()         bfin_read16(CAN1_AM19L)
#define bfin_write_CAN1_AM19L(val)     bfin_write16(CAN1_AM19L, val)
#define pCAN1_AM19H                    ((uint16_t volatile *)CAN1_AM19H) /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM19H()         bfin_read16(CAN1_AM19H)
#define bfin_write_CAN1_AM19H(val)     bfin_write16(CAN1_AM19H, val)
#define pCAN1_AM20L                    ((uint16_t volatile *)CAN1_AM20L) /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
#define bfin_read_CAN1_AM20L()         bfin_read16(CAN1_AM20L)
#define bfin_write_CAN1_AM20L(val)     bfin_write16(CAN1_AM20L, val)
#define pCAN1_AM20H                    ((uint16_t volatile *)CAN1_AM20H) /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM20H()         bfin_read16(CAN1_AM20H)
#define bfin_write_CAN1_AM20H(val)     bfin_write16(CAN1_AM20H, val)
#define pCAN1_AM21L                    ((uint16_t volatile *)CAN1_AM21L) /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
#define bfin_read_CAN1_AM21L()         bfin_read16(CAN1_AM21L)
#define bfin_write_CAN1_AM21L(val)     bfin_write16(CAN1_AM21L, val)
#define pCAN1_AM21H                    ((uint16_t volatile *)CAN1_AM21H) /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM21H()         bfin_read16(CAN1_AM21H)
#define bfin_write_CAN1_AM21H(val)     bfin_write16(CAN1_AM21H, val)
#define pCAN1_AM22L                    ((uint16_t volatile *)CAN1_AM22L) /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
#define bfin_read_CAN1_AM22L()         bfin_read16(CAN1_AM22L)
#define bfin_write_CAN1_AM22L(val)     bfin_write16(CAN1_AM22L, val)
#define pCAN1_AM22H                    ((uint16_t volatile *)CAN1_AM22H) /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM22H()         bfin_read16(CAN1_AM22H)
#define bfin_write_CAN1_AM22H(val)     bfin_write16(CAN1_AM22H, val)
#define pCAN1_AM23L                    ((uint16_t volatile *)CAN1_AM23L) /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
#define bfin_read_CAN1_AM23L()         bfin_read16(CAN1_AM23L)
#define bfin_write_CAN1_AM23L(val)     bfin_write16(CAN1_AM23L, val)
#define pCAN1_AM23H                    ((uint16_t volatile *)CAN1_AM23H) /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM23H()         bfin_read16(CAN1_AM23H)
#define bfin_write_CAN1_AM23H(val)     bfin_write16(CAN1_AM23H, val)
#define pCAN1_AM24L                    ((uint16_t volatile *)CAN1_AM24L) /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
#define bfin_read_CAN1_AM24L()         bfin_read16(CAN1_AM24L)
#define bfin_write_CAN1_AM24L(val)     bfin_write16(CAN1_AM24L, val)
#define pCAN1_AM24H                    ((uint16_t volatile *)CAN1_AM24H) /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM24H()         bfin_read16(CAN1_AM24H)
#define bfin_write_CAN1_AM24H(val)     bfin_write16(CAN1_AM24H, val)
#define pCAN1_AM25L                    ((uint16_t volatile *)CAN1_AM25L) /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
#define bfin_read_CAN1_AM25L()         bfin_read16(CAN1_AM25L)
#define bfin_write_CAN1_AM25L(val)     bfin_write16(CAN1_AM25L, val)
#define pCAN1_AM25H                    ((uint16_t volatile *)CAN1_AM25H) /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM25H()         bfin_read16(CAN1_AM25H)
#define bfin_write_CAN1_AM25H(val)     bfin_write16(CAN1_AM25H, val)
#define pCAN1_AM26L                    ((uint16_t volatile *)CAN1_AM26L) /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
#define bfin_read_CAN1_AM26L()         bfin_read16(CAN1_AM26L)
#define bfin_write_CAN1_AM26L(val)     bfin_write16(CAN1_AM26L, val)
#define pCAN1_AM26H                    ((uint16_t volatile *)CAN1_AM26H) /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM26H()         bfin_read16(CAN1_AM26H)
#define bfin_write_CAN1_AM26H(val)     bfin_write16(CAN1_AM26H, val)
#define pCAN1_AM27L                    ((uint16_t volatile *)CAN1_AM27L) /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
#define bfin_read_CAN1_AM27L()         bfin_read16(CAN1_AM27L)
#define bfin_write_CAN1_AM27L(val)     bfin_write16(CAN1_AM27L, val)
#define pCAN1_AM27H                    ((uint16_t volatile *)CAN1_AM27H) /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM27H()         bfin_read16(CAN1_AM27H)
#define bfin_write_CAN1_AM27H(val)     bfin_write16(CAN1_AM27H, val)
#define pCAN1_AM28L                    ((uint16_t volatile *)CAN1_AM28L) /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
#define bfin_read_CAN1_AM28L()         bfin_read16(CAN1_AM28L)
#define bfin_write_CAN1_AM28L(val)     bfin_write16(CAN1_AM28L, val)
#define pCAN1_AM28H                    ((uint16_t volatile *)CAN1_AM28H) /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM28H()         bfin_read16(CAN1_AM28H)
#define bfin_write_CAN1_AM28H(val)     bfin_write16(CAN1_AM28H, val)
#define pCAN1_AM29L                    ((uint16_t volatile *)CAN1_AM29L) /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
#define bfin_read_CAN1_AM29L()         bfin_read16(CAN1_AM29L)
#define bfin_write_CAN1_AM29L(val)     bfin_write16(CAN1_AM29L, val)
#define pCAN1_AM29H                    ((uint16_t volatile *)CAN1_AM29H) /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM29H()         bfin_read16(CAN1_AM29H)
#define bfin_write_CAN1_AM29H(val)     bfin_write16(CAN1_AM29H, val)
#define pCAN1_AM30L                    ((uint16_t volatile *)CAN1_AM30L) /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
#define bfin_read_CAN1_AM30L()         bfin_read16(CAN1_AM30L)
#define bfin_write_CAN1_AM30L(val)     bfin_write16(CAN1_AM30L, val)
#define pCAN1_AM30H                    ((uint16_t volatile *)CAN1_AM30H) /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM30H()         bfin_read16(CAN1_AM30H)
#define bfin_write_CAN1_AM30H(val)     bfin_write16(CAN1_AM30H, val)
#define pCAN1_AM31L                    ((uint16_t volatile *)CAN1_AM31L) /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
#define bfin_read_CAN1_AM31L()         bfin_read16(CAN1_AM31L)
#define bfin_write_CAN1_AM31L(val)     bfin_write16(CAN1_AM31L, val)
#define pCAN1_AM31H                    ((uint16_t volatile *)CAN1_AM31H) /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
#define bfin_read_CAN1_AM31H()         bfin_read16(CAN1_AM31H)
#define bfin_write_CAN1_AM31H(val)     bfin_write16(CAN1_AM31H, val)
#define pCAN1_MB00_DATA0               ((uint16_t volatile *)CAN1_MB00_DATA0) /* CAN Controller 1 Mailbox 0 Data 0 Register */
#define bfin_read_CAN1_MB00_DATA0()    bfin_read16(CAN1_MB00_DATA0)
#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
#define pCAN1_MB00_DATA1               ((uint16_t volatile *)CAN1_MB00_DATA1) /* CAN Controller 1 Mailbox 0 Data 1 Register */
#define bfin_read_CAN1_MB00_DATA1()    bfin_read16(CAN1_MB00_DATA1)
#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
#define pCAN1_MB00_DATA2               ((uint16_t volatile *)CAN1_MB00_DATA2) /* CAN Controller 1 Mailbox 0 Data 2 Register */
#define bfin_read_CAN1_MB00_DATA2()    bfin_read16(CAN1_MB00_DATA2)
#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
#define pCAN1_MB00_DATA3               ((uint16_t volatile *)CAN1_MB00_DATA3) /* CAN Controller 1 Mailbox 0 Data 3 Register */
#define bfin_read_CAN1_MB00_DATA3()    bfin_read16(CAN1_MB00_DATA3)
#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
#define pCAN1_MB00_LENGTH              ((uint16_t volatile *)CAN1_MB00_LENGTH) /* CAN Controller 1 Mailbox 0 Length Register */
#define bfin_read_CAN1_MB00_LENGTH()   bfin_read16(CAN1_MB00_LENGTH)
#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
#define pCAN1_MB00_TIMESTAMP           ((uint16_t volatile *)CAN1_MB00_TIMESTAMP) /* CAN Controller 1 Mailbox 0 Timestamp Register */
#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
#define pCAN1_MB00_ID0                 ((uint16_t volatile *)CAN1_MB00_ID0) /* CAN Controller 1 Mailbox 0 ID0 Register */
#define bfin_read_CAN1_MB00_ID0()      bfin_read16(CAN1_MB00_ID0)
#define bfin_write_CAN1_MB00_ID0(val)  bfin_write16(CAN1_MB00_ID0, val)
#define pCAN1_MB00_ID1                 ((uint16_t volatile *)CAN1_MB00_ID1) /* CAN Controller 1 Mailbox 0 ID1 Register */
#define bfin_read_CAN1_MB00_ID1()      bfin_read16(CAN1_MB00_ID1)
#define bfin_write_CAN1_MB00_ID1(val)  bfin_write16(CAN1_MB00_ID1, val)
#define pCAN1_MB01_DATA0               ((uint16_t volatile *)CAN1_MB01_DATA0) /* CAN Controller 1 Mailbox 1 Data 0 Register */
#define bfin_read_CAN1_MB01_DATA0()    bfin_read16(CAN1_MB01_DATA0)
#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
#define pCAN1_MB01_DATA1               ((uint16_t volatile *)CAN1_MB01_DATA1) /* CAN Controller 1 Mailbox 1 Data 1 Register */
#define bfin_read_CAN1_MB01_DATA1()    bfin_read16(CAN1_MB01_DATA1)
#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
#define pCAN1_MB01_DATA2               ((uint16_t volatile *)CAN1_MB01_DATA2) /* CAN Controller 1 Mailbox 1 Data 2 Register */
#define bfin_read_CAN1_MB01_DATA2()    bfin_read16(CAN1_MB01_DATA2)
#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
#define pCAN1_MB01_DATA3               ((uint16_t volatile *)CAN1_MB01_DATA3) /* CAN Controller 1 Mailbox 1 Data 3 Register */
#define bfin_read_CAN1_MB01_DATA3()    bfin_read16(CAN1_MB01_DATA3)
#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
#define pCAN1_MB01_LENGTH              ((uint16_t volatile *)CAN1_MB01_LENGTH) /* CAN Controller 1 Mailbox 1 Length Register */
#define bfin_read_CAN1_MB01_LENGTH()   bfin_read16(CAN1_MB01_LENGTH)
#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
#define pCAN1_MB01_TIMESTAMP           ((uint16_t volatile *)CAN1_MB01_TIMESTAMP) /* CAN Controller 1 Mailbox 1 Timestamp Register */
#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
#define pCAN1_MB01_ID0                 ((uint16_t volatile *)CAN1_MB01_ID0) /* CAN Controller 1 Mailbox 1 ID0 Register */
#define bfin_read_CAN1_MB01_ID0()      bfin_read16(CAN1_MB01_ID0)
#define bfin_write_CAN1_MB01_ID0(val)  bfin_write16(CAN1_MB01_ID0, val)
#define pCAN1_MB01_ID1                 ((uint16_t volatile *)CAN1_MB01_ID1) /* CAN Controller 1 Mailbox 1 ID1 Register */
#define bfin_read_CAN1_MB01_ID1()      bfin_read16(CAN1_MB01_ID1)
#define bfin_write_CAN1_MB01_ID1(val)  bfin_write16(CAN1_MB01_ID1, val)
#define pCAN1_MB02_DATA0               ((uint16_t volatile *)CAN1_MB02_DATA0) /* CAN Controller 1 Mailbox 2 Data 0 Register */
#define bfin_read_CAN1_MB02_DATA0()    bfin_read16(CAN1_MB02_DATA0)
#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
#define pCAN1_MB02_DATA1               ((uint16_t volatile *)CAN1_MB02_DATA1) /* CAN Controller 1 Mailbox 2 Data 1 Register */
#define bfin_read_CAN1_MB02_DATA1()    bfin_read16(CAN1_MB02_DATA1)
#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
#define pCAN1_MB02_DATA2               ((uint16_t volatile *)CAN1_MB02_DATA2) /* CAN Controller 1 Mailbox 2 Data 2 Register */
#define bfin_read_CAN1_MB02_DATA2()    bfin_read16(CAN1_MB02_DATA2)
#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
#define pCAN1_MB02_DATA3               ((uint16_t volatile *)CAN1_MB02_DATA3) /* CAN Controller 1 Mailbox 2 Data 3 Register */
#define bfin_read_CAN1_MB02_DATA3()    bfin_read16(CAN1_MB02_DATA3)
#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
#define pCAN1_MB02_LENGTH              ((uint16_t volatile *)CAN1_MB02_LENGTH) /* CAN Controller 1 Mailbox 2 Length Register */
#define bfin_read_CAN1_MB02_LENGTH()   bfin_read16(CAN1_MB02_LENGTH)
#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
#define pCAN1_MB02_TIMESTAMP           ((uint16_t volatile *)CAN1_MB02_TIMESTAMP) /* CAN Controller 1 Mailbox 2 Timestamp Register */
#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
#define pCAN1_MB02_ID0                 ((uint16_t volatile *)CAN1_MB02_ID0) /* CAN Controller 1 Mailbox 2 ID0 Register */
#define bfin_read_CAN1_MB02_ID0()      bfin_read16(CAN1_MB02_ID0)
#define bfin_write_CAN1_MB02_ID0(val)  bfin_write16(CAN1_MB02_ID0, val)
#define pCAN1_MB02_ID1                 ((uint16_t volatile *)CAN1_MB02_ID1) /* CAN Controller 1 Mailbox 2 ID1 Register */
#define bfin_read_CAN1_MB02_ID1()      bfin_read16(CAN1_MB02_ID1)
#define bfin_write_CAN1_MB02_ID1(val)  bfin_write16(CAN1_MB02_ID1, val)
#define pCAN1_MB03_DATA0               ((uint16_t volatile *)CAN1_MB03_DATA0) /* CAN Controller 1 Mailbox 3 Data 0 Register */
#define bfin_read_CAN1_MB03_DATA0()    bfin_read16(CAN1_MB03_DATA0)
#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
#define pCAN1_MB03_DATA1               ((uint16_t volatile *)CAN1_MB03_DATA1) /* CAN Controller 1 Mailbox 3 Data 1 Register */
#define bfin_read_CAN1_MB03_DATA1()    bfin_read16(CAN1_MB03_DATA1)
#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
#define pCAN1_MB03_DATA2               ((uint16_t volatile *)CAN1_MB03_DATA2) /* CAN Controller 1 Mailbox 3 Data 2 Register */
#define bfin_read_CAN1_MB03_DATA2()    bfin_read16(CAN1_MB03_DATA2)
#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
#define pCAN1_MB03_DATA3               ((uint16_t volatile *)CAN1_MB03_DATA3) /* CAN Controller 1 Mailbox 3 Data 3 Register */
#define bfin_read_CAN1_MB03_DATA3()    bfin_read16(CAN1_MB03_DATA3)
#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
#define pCAN1_MB03_LENGTH              ((uint16_t volatile *)CAN1_MB03_LENGTH) /* CAN Controller 1 Mailbox 3 Length Register */
#define bfin_read_CAN1_MB03_LENGTH()   bfin_read16(CAN1_MB03_LENGTH)
#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
#define pCAN1_MB03_TIMESTAMP           ((uint16_t volatile *)CAN1_MB03_TIMESTAMP) /* CAN Controller 1 Mailbox 3 Timestamp Register */
#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
#define pCAN1_MB03_ID0                 ((uint16_t volatile *)CAN1_MB03_ID0) /* CAN Controller 1 Mailbox 3 ID0 Register */
#define bfin_read_CAN1_MB03_ID0()      bfin_read16(CAN1_MB03_ID0)
#define bfin_write_CAN1_MB03_ID0(val)  bfin_write16(CAN1_MB03_ID0, val)
#define pCAN1_MB03_ID1                 ((uint16_t volatile *)CAN1_MB03_ID1) /* CAN Controller 1 Mailbox 3 ID1 Register */
#define bfin_read_CAN1_MB03_ID1()      bfin_read16(CAN1_MB03_ID1)
#define bfin_write_CAN1_MB03_ID1(val)  bfin_write16(CAN1_MB03_ID1, val)
#define pCAN1_MB04_DATA0               ((uint16_t volatile *)CAN1_MB04_DATA0) /* CAN Controller 1 Mailbox 4 Data 0 Register */
#define bfin_read_CAN1_MB04_DATA0()    bfin_read16(CAN1_MB04_DATA0)
#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
#define pCAN1_MB04_DATA1               ((uint16_t volatile *)CAN1_MB04_DATA1) /* CAN Controller 1 Mailbox 4 Data 1 Register */
#define bfin_read_CAN1_MB04_DATA1()    bfin_read16(CAN1_MB04_DATA1)
#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
#define pCAN1_MB04_DATA2               ((uint16_t volatile *)CAN1_MB04_DATA2) /* CAN Controller 1 Mailbox 4 Data 2 Register */
#define bfin_read_CAN1_MB04_DATA2()    bfin_read16(CAN1_MB04_DATA2)
#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
#define pCAN1_MB04_DATA3               ((uint16_t volatile *)CAN1_MB04_DATA3) /* CAN Controller 1 Mailbox 4 Data 3 Register */
#define bfin_read_CAN1_MB04_DATA3()    bfin_read16(CAN1_MB04_DATA3)
#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
#define pCAN1_MB04_LENGTH              ((uint16_t volatile *)CAN1_MB04_LENGTH) /* CAN Controller 1 Mailbox 4 Length Register */
#define bfin_read_CAN1_MB04_LENGTH()   bfin_read16(CAN1_MB04_LENGTH)
#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
#define pCAN1_MB04_TIMESTAMP           ((uint16_t volatile *)CAN1_MB04_TIMESTAMP) /* CAN Controller 1 Mailbox 4 Timestamp Register */
#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
#define pCAN1_MB04_ID0                 ((uint16_t volatile *)CAN1_MB04_ID0) /* CAN Controller 1 Mailbox 4 ID0 Register */
#define bfin_read_CAN1_MB04_ID0()      bfin_read16(CAN1_MB04_ID0)
#define bfin_write_CAN1_MB04_ID0(val)  bfin_write16(CAN1_MB04_ID0, val)
#define pCAN1_MB04_ID1                 ((uint16_t volatile *)CAN1_MB04_ID1) /* CAN Controller 1 Mailbox 4 ID1 Register */
#define bfin_read_CAN1_MB04_ID1()      bfin_read16(CAN1_MB04_ID1)
#define bfin_write_CAN1_MB04_ID1(val)  bfin_write16(CAN1_MB04_ID1, val)
#define pCAN1_MB05_DATA0               ((uint16_t volatile *)CAN1_MB05_DATA0) /* CAN Controller 1 Mailbox 5 Data 0 Register */
#define bfin_read_CAN1_MB05_DATA0()    bfin_read16(CAN1_MB05_DATA0)
#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
#define pCAN1_MB05_DATA1               ((uint16_t volatile *)CAN1_MB05_DATA1) /* CAN Controller 1 Mailbox 5 Data 1 Register */
#define bfin_read_CAN1_MB05_DATA1()    bfin_read16(CAN1_MB05_DATA1)
#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
#define pCAN1_MB05_DATA2               ((uint16_t volatile *)CAN1_MB05_DATA2) /* CAN Controller 1 Mailbox 5 Data 2 Register */
#define bfin_read_CAN1_MB05_DATA2()    bfin_read16(CAN1_MB05_DATA2)
#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
#define pCAN1_MB05_DATA3               ((uint16_t volatile *)CAN1_MB05_DATA3) /* CAN Controller 1 Mailbox 5 Data 3 Register */
#define bfin_read_CAN1_MB05_DATA3()    bfin_read16(CAN1_MB05_DATA3)
#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
#define pCAN1_MB05_LENGTH              ((uint16_t volatile *)CAN1_MB05_LENGTH) /* CAN Controller 1 Mailbox 5 Length Register */
#define bfin_read_CAN1_MB05_LENGTH()   bfin_read16(CAN1_MB05_LENGTH)
#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
#define pCAN1_MB05_TIMESTAMP           ((uint16_t volatile *)CAN1_MB05_TIMESTAMP) /* CAN Controller 1 Mailbox 5 Timestamp Register */
#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
#define pCAN1_MB05_ID0                 ((uint16_t volatile *)CAN1_MB05_ID0) /* CAN Controller 1 Mailbox 5 ID0 Register */
#define bfin_read_CAN1_MB05_ID0()      bfin_read16(CAN1_MB05_ID0)
#define bfin_write_CAN1_MB05_ID0(val)  bfin_write16(CAN1_MB05_ID0, val)
#define pCAN1_MB05_ID1                 ((uint16_t volatile *)CAN1_MB05_ID1) /* CAN Controller 1 Mailbox 5 ID1 Register */
#define bfin_read_CAN1_MB05_ID1()      bfin_read16(CAN1_MB05_ID1)
#define bfin_write_CAN1_MB05_ID1(val)  bfin_write16(CAN1_MB05_ID1, val)
#define pCAN1_MB06_DATA0               ((uint16_t volatile *)CAN1_MB06_DATA0) /* CAN Controller 1 Mailbox 6 Data 0 Register */
#define bfin_read_CAN1_MB06_DATA0()    bfin_read16(CAN1_MB06_DATA0)
#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
#define pCAN1_MB06_DATA1               ((uint16_t volatile *)CAN1_MB06_DATA1) /* CAN Controller 1 Mailbox 6 Data 1 Register */
#define bfin_read_CAN1_MB06_DATA1()    bfin_read16(CAN1_MB06_DATA1)
#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
#define pCAN1_MB06_DATA2               ((uint16_t volatile *)CAN1_MB06_DATA2) /* CAN Controller 1 Mailbox 6 Data 2 Register */
#define bfin_read_CAN1_MB06_DATA2()    bfin_read16(CAN1_MB06_DATA2)
#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
#define pCAN1_MB06_DATA3               ((uint16_t volatile *)CAN1_MB06_DATA3) /* CAN Controller 1 Mailbox 6 Data 3 Register */
#define bfin_read_CAN1_MB06_DATA3()    bfin_read16(CAN1_MB06_DATA3)
#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
#define pCAN1_MB06_LENGTH              ((uint16_t volatile *)CAN1_MB06_LENGTH) /* CAN Controller 1 Mailbox 6 Length Register */
#define bfin_read_CAN1_MB06_LENGTH()   bfin_read16(CAN1_MB06_LENGTH)
#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
#define pCAN1_MB06_TIMESTAMP           ((uint16_t volatile *)CAN1_MB06_TIMESTAMP) /* CAN Controller 1 Mailbox 6 Timestamp Register */
#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
#define pCAN1_MB06_ID0                 ((uint16_t volatile *)CAN1_MB06_ID0) /* CAN Controller 1 Mailbox 6 ID0 Register */
#define bfin_read_CAN1_MB06_ID0()      bfin_read16(CAN1_MB06_ID0)
#define bfin_write_CAN1_MB06_ID0(val)  bfin_write16(CAN1_MB06_ID0, val)
#define pCAN1_MB06_ID1                 ((uint16_t volatile *)CAN1_MB06_ID1) /* CAN Controller 1 Mailbox 6 ID1 Register */
#define bfin_read_CAN1_MB06_ID1()      bfin_read16(CAN1_MB06_ID1)
#define bfin_write_CAN1_MB06_ID1(val)  bfin_write16(CAN1_MB06_ID1, val)
#define pCAN1_MB07_DATA0               ((uint16_t volatile *)CAN1_MB07_DATA0) /* CAN Controller 1 Mailbox 7 Data 0 Register */
#define bfin_read_CAN1_MB07_DATA0()    bfin_read16(CAN1_MB07_DATA0)
#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
#define pCAN1_MB07_DATA1               ((uint16_t volatile *)CAN1_MB07_DATA1) /* CAN Controller 1 Mailbox 7 Data 1 Register */
#define bfin_read_CAN1_MB07_DATA1()    bfin_read16(CAN1_MB07_DATA1)
#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
#define pCAN1_MB07_DATA2               ((uint16_t volatile *)CAN1_MB07_DATA2) /* CAN Controller 1 Mailbox 7 Data 2 Register */
#define bfin_read_CAN1_MB07_DATA2()    bfin_read16(CAN1_MB07_DATA2)
#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
#define pCAN1_MB07_DATA3               ((uint16_t volatile *)CAN1_MB07_DATA3) /* CAN Controller 1 Mailbox 7 Data 3 Register */
#define bfin_read_CAN1_MB07_DATA3()    bfin_read16(CAN1_MB07_DATA3)
#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
#define pCAN1_MB07_LENGTH              ((uint16_t volatile *)CAN1_MB07_LENGTH) /* CAN Controller 1 Mailbox 7 Length Register */
#define bfin_read_CAN1_MB07_LENGTH()   bfin_read16(CAN1_MB07_LENGTH)
#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
#define pCAN1_MB07_TIMESTAMP           ((uint16_t volatile *)CAN1_MB07_TIMESTAMP) /* CAN Controller 1 Mailbox 7 Timestamp Register */
#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
#define pCAN1_MB07_ID0                 ((uint16_t volatile *)CAN1_MB07_ID0) /* CAN Controller 1 Mailbox 7 ID0 Register */
#define bfin_read_CAN1_MB07_ID0()      bfin_read16(CAN1_MB07_ID0)
#define bfin_write_CAN1_MB07_ID0(val)  bfin_write16(CAN1_MB07_ID0, val)
#define pCAN1_MB07_ID1                 ((uint16_t volatile *)CAN1_MB07_ID1) /* CAN Controller 1 Mailbox 7 ID1 Register */
#define bfin_read_CAN1_MB07_ID1()      bfin_read16(CAN1_MB07_ID1)
#define bfin_write_CAN1_MB07_ID1(val)  bfin_write16(CAN1_MB07_ID1, val)
#define pCAN1_MB08_DATA0               ((uint16_t volatile *)CAN1_MB08_DATA0) /* CAN Controller 1 Mailbox 8 Data 0 Register */
#define bfin_read_CAN1_MB08_DATA0()    bfin_read16(CAN1_MB08_DATA0)
#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
#define pCAN1_MB08_DATA1               ((uint16_t volatile *)CAN1_MB08_DATA1) /* CAN Controller 1 Mailbox 8 Data 1 Register */
#define bfin_read_CAN1_MB08_DATA1()    bfin_read16(CAN1_MB08_DATA1)
#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
#define pCAN1_MB08_DATA2               ((uint16_t volatile *)CAN1_MB08_DATA2) /* CAN Controller 1 Mailbox 8 Data 2 Register */
#define bfin_read_CAN1_MB08_DATA2()    bfin_read16(CAN1_MB08_DATA2)
#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
#define pCAN1_MB08_DATA3               ((uint16_t volatile *)CAN1_MB08_DATA3) /* CAN Controller 1 Mailbox 8 Data 3 Register */
#define bfin_read_CAN1_MB08_DATA3()    bfin_read16(CAN1_MB08_DATA3)
#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
#define pCAN1_MB08_LENGTH              ((uint16_t volatile *)CAN1_MB08_LENGTH) /* CAN Controller 1 Mailbox 8 Length Register */
#define bfin_read_CAN1_MB08_LENGTH()   bfin_read16(CAN1_MB08_LENGTH)
#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
#define pCAN1_MB08_TIMESTAMP           ((uint16_t volatile *)CAN1_MB08_TIMESTAMP) /* CAN Controller 1 Mailbox 8 Timestamp Register */
#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
#define pCAN1_MB08_ID0                 ((uint16_t volatile *)CAN1_MB08_ID0) /* CAN Controller 1 Mailbox 8 ID0 Register */
#define bfin_read_CAN1_MB08_ID0()      bfin_read16(CAN1_MB08_ID0)
#define bfin_write_CAN1_MB08_ID0(val)  bfin_write16(CAN1_MB08_ID0, val)
#define pCAN1_MB08_ID1                 ((uint16_t volatile *)CAN1_MB08_ID1) /* CAN Controller 1 Mailbox 8 ID1 Register */
#define bfin_read_CAN1_MB08_ID1()      bfin_read16(CAN1_MB08_ID1)
#define bfin_write_CAN1_MB08_ID1(val)  bfin_write16(CAN1_MB08_ID1, val)
#define pCAN1_MB09_DATA0               ((uint16_t volatile *)CAN1_MB09_DATA0) /* CAN Controller 1 Mailbox 9 Data 0 Register */
#define bfin_read_CAN1_MB09_DATA0()    bfin_read16(CAN1_MB09_DATA0)
#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
#define pCAN1_MB09_DATA1               ((uint16_t volatile *)CAN1_MB09_DATA1) /* CAN Controller 1 Mailbox 9 Data 1 Register */
#define bfin_read_CAN1_MB09_DATA1()    bfin_read16(CAN1_MB09_DATA1)
#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
#define pCAN1_MB09_DATA2               ((uint16_t volatile *)CAN1_MB09_DATA2) /* CAN Controller 1 Mailbox 9 Data 2 Register */
#define bfin_read_CAN1_MB09_DATA2()    bfin_read16(CAN1_MB09_DATA2)
#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
#define pCAN1_MB09_DATA3               ((uint16_t volatile *)CAN1_MB09_DATA3) /* CAN Controller 1 Mailbox 9 Data 3 Register */
#define bfin_read_CAN1_MB09_DATA3()    bfin_read16(CAN1_MB09_DATA3)
#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
#define pCAN1_MB09_LENGTH              ((uint16_t volatile *)CAN1_MB09_LENGTH) /* CAN Controller 1 Mailbox 9 Length Register */
#define bfin_read_CAN1_MB09_LENGTH()   bfin_read16(CAN1_MB09_LENGTH)
#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
#define pCAN1_MB09_TIMESTAMP           ((uint16_t volatile *)CAN1_MB09_TIMESTAMP) /* CAN Controller 1 Mailbox 9 Timestamp Register */
#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
#define pCAN1_MB09_ID0                 ((uint16_t volatile *)CAN1_MB09_ID0) /* CAN Controller 1 Mailbox 9 ID0 Register */
#define bfin_read_CAN1_MB09_ID0()      bfin_read16(CAN1_MB09_ID0)
#define bfin_write_CAN1_MB09_ID0(val)  bfin_write16(CAN1_MB09_ID0, val)
#define pCAN1_MB09_ID1                 ((uint16_t volatile *)CAN1_MB09_ID1) /* CAN Controller 1 Mailbox 9 ID1 Register */
#define bfin_read_CAN1_MB09_ID1()      bfin_read16(CAN1_MB09_ID1)
#define bfin_write_CAN1_MB09_ID1(val)  bfin_write16(CAN1_MB09_ID1, val)
#define pCAN1_MB10_DATA0               ((uint16_t volatile *)CAN1_MB10_DATA0) /* CAN Controller 1 Mailbox 10 Data 0 Register */
#define bfin_read_CAN1_MB10_DATA0()    bfin_read16(CAN1_MB10_DATA0)
#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
#define pCAN1_MB10_DATA1               ((uint16_t volatile *)CAN1_MB10_DATA1) /* CAN Controller 1 Mailbox 10 Data 1 Register */
#define bfin_read_CAN1_MB10_DATA1()    bfin_read16(CAN1_MB10_DATA1)
#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
#define pCAN1_MB10_DATA2               ((uint16_t volatile *)CAN1_MB10_DATA2) /* CAN Controller 1 Mailbox 10 Data 2 Register */
#define bfin_read_CAN1_MB10_DATA2()    bfin_read16(CAN1_MB10_DATA2)
#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
#define pCAN1_MB10_DATA3               ((uint16_t volatile *)CAN1_MB10_DATA3) /* CAN Controller 1 Mailbox 10 Data 3 Register */
#define bfin_read_CAN1_MB10_DATA3()    bfin_read16(CAN1_MB10_DATA3)
#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
#define pCAN1_MB10_LENGTH              ((uint16_t volatile *)CAN1_MB10_LENGTH) /* CAN Controller 1 Mailbox 10 Length Register */
#define bfin_read_CAN1_MB10_LENGTH()   bfin_read16(CAN1_MB10_LENGTH)
#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
#define pCAN1_MB10_TIMESTAMP           ((uint16_t volatile *)CAN1_MB10_TIMESTAMP) /* CAN Controller 1 Mailbox 10 Timestamp Register */
#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
#define pCAN1_MB10_ID0                 ((uint16_t volatile *)CAN1_MB10_ID0) /* CAN Controller 1 Mailbox 10 ID0 Register */
#define bfin_read_CAN1_MB10_ID0()      bfin_read16(CAN1_MB10_ID0)
#define bfin_write_CAN1_MB10_ID0(val)  bfin_write16(CAN1_MB10_ID0, val)
#define pCAN1_MB10_ID1                 ((uint16_t volatile *)CAN1_MB10_ID1) /* CAN Controller 1 Mailbox 10 ID1 Register */
#define bfin_read_CAN1_MB10_ID1()      bfin_read16(CAN1_MB10_ID1)
#define bfin_write_CAN1_MB10_ID1(val)  bfin_write16(CAN1_MB10_ID1, val)
#define pCAN1_MB11_DATA0               ((uint16_t volatile *)CAN1_MB11_DATA0) /* CAN Controller 1 Mailbox 11 Data 0 Register */
#define bfin_read_CAN1_MB11_DATA0()    bfin_read16(CAN1_MB11_DATA0)
#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
#define pCAN1_MB11_DATA1               ((uint16_t volatile *)CAN1_MB11_DATA1) /* CAN Controller 1 Mailbox 11 Data 1 Register */
#define bfin_read_CAN1_MB11_DATA1()    bfin_read16(CAN1_MB11_DATA1)
#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
#define pCAN1_MB11_DATA2               ((uint16_t volatile *)CAN1_MB11_DATA2) /* CAN Controller 1 Mailbox 11 Data 2 Register */
#define bfin_read_CAN1_MB11_DATA2()    bfin_read16(CAN1_MB11_DATA2)
#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
#define pCAN1_MB11_DATA3               ((uint16_t volatile *)CAN1_MB11_DATA3) /* CAN Controller 1 Mailbox 11 Data 3 Register */
#define bfin_read_CAN1_MB11_DATA3()    bfin_read16(CAN1_MB11_DATA3)
#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
#define pCAN1_MB11_LENGTH              ((uint16_t volatile *)CAN1_MB11_LENGTH) /* CAN Controller 1 Mailbox 11 Length Register */
#define bfin_read_CAN1_MB11_LENGTH()   bfin_read16(CAN1_MB11_LENGTH)
#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
#define pCAN1_MB11_TIMESTAMP           ((uint16_t volatile *)CAN1_MB11_TIMESTAMP) /* CAN Controller 1 Mailbox 11 Timestamp Register */
#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
#define pCAN1_MB11_ID0                 ((uint16_t volatile *)CAN1_MB11_ID0) /* CAN Controller 1 Mailbox 11 ID0 Register */
#define bfin_read_CAN1_MB11_ID0()      bfin_read16(CAN1_MB11_ID0)
#define bfin_write_CAN1_MB11_ID0(val)  bfin_write16(CAN1_MB11_ID0, val)
#define pCAN1_MB11_ID1                 ((uint16_t volatile *)CAN1_MB11_ID1) /* CAN Controller 1 Mailbox 11 ID1 Register */
#define bfin_read_CAN1_MB11_ID1()      bfin_read16(CAN1_MB11_ID1)
#define bfin_write_CAN1_MB11_ID1(val)  bfin_write16(CAN1_MB11_ID1, val)
#define pCAN1_MB12_DATA0               ((uint16_t volatile *)CAN1_MB12_DATA0) /* CAN Controller 1 Mailbox 12 Data 0 Register */
#define bfin_read_CAN1_MB12_DATA0()    bfin_read16(CAN1_MB12_DATA0)
#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
#define pCAN1_MB12_DATA1               ((uint16_t volatile *)CAN1_MB12_DATA1) /* CAN Controller 1 Mailbox 12 Data 1 Register */
#define bfin_read_CAN1_MB12_DATA1()    bfin_read16(CAN1_MB12_DATA1)
#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
#define pCAN1_MB12_DATA2               ((uint16_t volatile *)CAN1_MB12_DATA2) /* CAN Controller 1 Mailbox 12 Data 2 Register */
#define bfin_read_CAN1_MB12_DATA2()    bfin_read16(CAN1_MB12_DATA2)
#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
#define pCAN1_MB12_DATA3               ((uint16_t volatile *)CAN1_MB12_DATA3) /* CAN Controller 1 Mailbox 12 Data 3 Register */
#define bfin_read_CAN1_MB12_DATA3()    bfin_read16(CAN1_MB12_DATA3)
#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
#define pCAN1_MB12_LENGTH              ((uint16_t volatile *)CAN1_MB12_LENGTH) /* CAN Controller 1 Mailbox 12 Length Register */
#define bfin_read_CAN1_MB12_LENGTH()   bfin_read16(CAN1_MB12_LENGTH)
#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
#define pCAN1_MB12_TIMESTAMP           ((uint16_t volatile *)CAN1_MB12_TIMESTAMP) /* CAN Controller 1 Mailbox 12 Timestamp Register */
#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
#define pCAN1_MB12_ID0                 ((uint16_t volatile *)CAN1_MB12_ID0) /* CAN Controller 1 Mailbox 12 ID0 Register */
#define bfin_read_CAN1_MB12_ID0()      bfin_read16(CAN1_MB12_ID0)
#define bfin_write_CAN1_MB12_ID0(val)  bfin_write16(CAN1_MB12_ID0, val)
#define pCAN1_MB12_ID1                 ((uint16_t volatile *)CAN1_MB12_ID1) /* CAN Controller 1 Mailbox 12 ID1 Register */
#define bfin_read_CAN1_MB12_ID1()      bfin_read16(CAN1_MB12_ID1)
#define bfin_write_CAN1_MB12_ID1(val)  bfin_write16(CAN1_MB12_ID1, val)
#define pCAN1_MB13_DATA0               ((uint16_t volatile *)CAN1_MB13_DATA0) /* CAN Controller 1 Mailbox 13 Data 0 Register */
#define bfin_read_CAN1_MB13_DATA0()    bfin_read16(CAN1_MB13_DATA0)
#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
#define pCAN1_MB13_DATA1               ((uint16_t volatile *)CAN1_MB13_DATA1) /* CAN Controller 1 Mailbox 13 Data 1 Register */
#define bfin_read_CAN1_MB13_DATA1()    bfin_read16(CAN1_MB13_DATA1)
#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
#define pCAN1_MB13_DATA2               ((uint16_t volatile *)CAN1_MB13_DATA2) /* CAN Controller 1 Mailbox 13 Data 2 Register */
#define bfin_read_CAN1_MB13_DATA2()    bfin_read16(CAN1_MB13_DATA2)
#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
#define pCAN1_MB13_DATA3               ((uint16_t volatile *)CAN1_MB13_DATA3) /* CAN Controller 1 Mailbox 13 Data 3 Register */
#define bfin_read_CAN1_MB13_DATA3()    bfin_read16(CAN1_MB13_DATA3)
#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
#define pCAN1_MB13_LENGTH              ((uint16_t volatile *)CAN1_MB13_LENGTH) /* CAN Controller 1 Mailbox 13 Length Register */
#define bfin_read_CAN1_MB13_LENGTH()   bfin_read16(CAN1_MB13_LENGTH)
#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
#define pCAN1_MB13_TIMESTAMP           ((uint16_t volatile *)CAN1_MB13_TIMESTAMP) /* CAN Controller 1 Mailbox 13 Timestamp Register */
#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
#define pCAN1_MB13_ID0                 ((uint16_t volatile *)CAN1_MB13_ID0) /* CAN Controller 1 Mailbox 13 ID0 Register */
#define bfin_read_CAN1_MB13_ID0()      bfin_read16(CAN1_MB13_ID0)
#define bfin_write_CAN1_MB13_ID0(val)  bfin_write16(CAN1_MB13_ID0, val)
#define pCAN1_MB13_ID1                 ((uint16_t volatile *)CAN1_MB13_ID1) /* CAN Controller 1 Mailbox 13 ID1 Register */
#define bfin_read_CAN1_MB13_ID1()      bfin_read16(CAN1_MB13_ID1)
#define bfin_write_CAN1_MB13_ID1(val)  bfin_write16(CAN1_MB13_ID1, val)
#define pCAN1_MB14_DATA0               ((uint16_t volatile *)CAN1_MB14_DATA0) /* CAN Controller 1 Mailbox 14 Data 0 Register */
#define bfin_read_CAN1_MB14_DATA0()    bfin_read16(CAN1_MB14_DATA0)
#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
#define pCAN1_MB14_DATA1               ((uint16_t volatile *)CAN1_MB14_DATA1) /* CAN Controller 1 Mailbox 14 Data 1 Register */
#define bfin_read_CAN1_MB14_DATA1()    bfin_read16(CAN1_MB14_DATA1)
#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
#define pCAN1_MB14_DATA2               ((uint16_t volatile *)CAN1_MB14_DATA2) /* CAN Controller 1 Mailbox 14 Data 2 Register */
#define bfin_read_CAN1_MB14_DATA2()    bfin_read16(CAN1_MB14_DATA2)
#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
#define pCAN1_MB14_DATA3               ((uint16_t volatile *)CAN1_MB14_DATA3) /* CAN Controller 1 Mailbox 14 Data 3 Register */
#define bfin_read_CAN1_MB14_DATA3()    bfin_read16(CAN1_MB14_DATA3)
#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
#define pCAN1_MB14_LENGTH              ((uint16_t volatile *)CAN1_MB14_LENGTH) /* CAN Controller 1 Mailbox 14 Length Register */
#define bfin_read_CAN1_MB14_LENGTH()   bfin_read16(CAN1_MB14_LENGTH)
#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
#define pCAN1_MB14_TIMESTAMP           ((uint16_t volatile *)CAN1_MB14_TIMESTAMP) /* CAN Controller 1 Mailbox 14 Timestamp Register */
#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
#define pCAN1_MB14_ID0                 ((uint16_t volatile *)CAN1_MB14_ID0) /* CAN Controller 1 Mailbox 14 ID0 Register */
#define bfin_read_CAN1_MB14_ID0()      bfin_read16(CAN1_MB14_ID0)
#define bfin_write_CAN1_MB14_ID0(val)  bfin_write16(CAN1_MB14_ID0, val)
#define pCAN1_MB14_ID1                 ((uint16_t volatile *)CAN1_MB14_ID1) /* CAN Controller 1 Mailbox 14 ID1 Register */
#define bfin_read_CAN1_MB14_ID1()      bfin_read16(CAN1_MB14_ID1)
#define bfin_write_CAN1_MB14_ID1(val)  bfin_write16(CAN1_MB14_ID1, val)
#define pCAN1_MB15_DATA0               ((uint16_t volatile *)CAN1_MB15_DATA0) /* CAN Controller 1 Mailbox 15 Data 0 Register */
#define bfin_read_CAN1_MB15_DATA0()    bfin_read16(CAN1_MB15_DATA0)
#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
#define pCAN1_MB15_DATA1               ((uint16_t volatile *)CAN1_MB15_DATA1) /* CAN Controller 1 Mailbox 15 Data 1 Register */
#define bfin_read_CAN1_MB15_DATA1()    bfin_read16(CAN1_MB15_DATA1)
#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
#define pCAN1_MB15_DATA2               ((uint16_t volatile *)CAN1_MB15_DATA2) /* CAN Controller 1 Mailbox 15 Data 2 Register */
#define bfin_read_CAN1_MB15_DATA2()    bfin_read16(CAN1_MB15_DATA2)
#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
#define pCAN1_MB15_DATA3               ((uint16_t volatile *)CAN1_MB15_DATA3) /* CAN Controller 1 Mailbox 15 Data 3 Register */
#define bfin_read_CAN1_MB15_DATA3()    bfin_read16(CAN1_MB15_DATA3)
#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
#define pCAN1_MB15_LENGTH              ((uint16_t volatile *)CAN1_MB15_LENGTH) /* CAN Controller 1 Mailbox 15 Length Register */
#define bfin_read_CAN1_MB15_LENGTH()   bfin_read16(CAN1_MB15_LENGTH)
#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
#define pCAN1_MB15_TIMESTAMP           ((uint16_t volatile *)CAN1_MB15_TIMESTAMP) /* CAN Controller 1 Mailbox 15 Timestamp Register */
#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
#define pCAN1_MB15_ID0                 ((uint16_t volatile *)CAN1_MB15_ID0) /* CAN Controller 1 Mailbox 15 ID0 Register */
#define bfin_read_CAN1_MB15_ID0()      bfin_read16(CAN1_MB15_ID0)
#define bfin_write_CAN1_MB15_ID0(val)  bfin_write16(CAN1_MB15_ID0, val)
#define pCAN1_MB15_ID1                 ((uint16_t volatile *)CAN1_MB15_ID1) /* CAN Controller 1 Mailbox 15 ID1 Register */
#define bfin_read_CAN1_MB15_ID1()      bfin_read16(CAN1_MB15_ID1)
#define bfin_write_CAN1_MB15_ID1(val)  bfin_write16(CAN1_MB15_ID1, val)
#define pCAN1_MB16_DATA0               ((uint16_t volatile *)CAN1_MB16_DATA0) /* CAN Controller 1 Mailbox 16 Data 0 Register */
#define bfin_read_CAN1_MB16_DATA0()    bfin_read16(CAN1_MB16_DATA0)
#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
#define pCAN1_MB16_DATA1               ((uint16_t volatile *)CAN1_MB16_DATA1) /* CAN Controller 1 Mailbox 16 Data 1 Register */
#define bfin_read_CAN1_MB16_DATA1()    bfin_read16(CAN1_MB16_DATA1)
#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
#define pCAN1_MB16_DATA2               ((uint16_t volatile *)CAN1_MB16_DATA2) /* CAN Controller 1 Mailbox 16 Data 2 Register */
#define bfin_read_CAN1_MB16_DATA2()    bfin_read16(CAN1_MB16_DATA2)
#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
#define pCAN1_MB16_DATA3               ((uint16_t volatile *)CAN1_MB16_DATA3) /* CAN Controller 1 Mailbox 16 Data 3 Register */
#define bfin_read_CAN1_MB16_DATA3()    bfin_read16(CAN1_MB16_DATA3)
#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
#define pCAN1_MB16_LENGTH              ((uint16_t volatile *)CAN1_MB16_LENGTH) /* CAN Controller 1 Mailbox 16 Length Register */
#define bfin_read_CAN1_MB16_LENGTH()   bfin_read16(CAN1_MB16_LENGTH)
#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
#define pCAN1_MB16_TIMESTAMP           ((uint16_t volatile *)CAN1_MB16_TIMESTAMP) /* CAN Controller 1 Mailbox 16 Timestamp Register */
#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
#define pCAN1_MB16_ID0                 ((uint16_t volatile *)CAN1_MB16_ID0) /* CAN Controller 1 Mailbox 16 ID0 Register */
#define bfin_read_CAN1_MB16_ID0()      bfin_read16(CAN1_MB16_ID0)
#define bfin_write_CAN1_MB16_ID0(val)  bfin_write16(CAN1_MB16_ID0, val)
#define pCAN1_MB16_ID1                 ((uint16_t volatile *)CAN1_MB16_ID1) /* CAN Controller 1 Mailbox 16 ID1 Register */
#define bfin_read_CAN1_MB16_ID1()      bfin_read16(CAN1_MB16_ID1)
#define bfin_write_CAN1_MB16_ID1(val)  bfin_write16(CAN1_MB16_ID1, val)
#define pCAN1_MB17_DATA0               ((uint16_t volatile *)CAN1_MB17_DATA0) /* CAN Controller 1 Mailbox 17 Data 0 Register */
#define bfin_read_CAN1_MB17_DATA0()    bfin_read16(CAN1_MB17_DATA0)
#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
#define pCAN1_MB17_DATA1               ((uint16_t volatile *)CAN1_MB17_DATA1) /* CAN Controller 1 Mailbox 17 Data 1 Register */
#define bfin_read_CAN1_MB17_DATA1()    bfin_read16(CAN1_MB17_DATA1)
#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
#define pCAN1_MB17_DATA2               ((uint16_t volatile *)CAN1_MB17_DATA2) /* CAN Controller 1 Mailbox 17 Data 2 Register */
#define bfin_read_CAN1_MB17_DATA2()    bfin_read16(CAN1_MB17_DATA2)
#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
#define pCAN1_MB17_DATA3               ((uint16_t volatile *)CAN1_MB17_DATA3) /* CAN Controller 1 Mailbox 17 Data 3 Register */
#define bfin_read_CAN1_MB17_DATA3()    bfin_read16(CAN1_MB17_DATA3)
#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
#define pCAN1_MB17_LENGTH              ((uint16_t volatile *)CAN1_MB17_LENGTH) /* CAN Controller 1 Mailbox 17 Length Register */
#define bfin_read_CAN1_MB17_LENGTH()   bfin_read16(CAN1_MB17_LENGTH)
#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
#define pCAN1_MB17_TIMESTAMP           ((uint16_t volatile *)CAN1_MB17_TIMESTAMP) /* CAN Controller 1 Mailbox 17 Timestamp Register */
#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
#define pCAN1_MB17_ID0                 ((uint16_t volatile *)CAN1_MB17_ID0) /* CAN Controller 1 Mailbox 17 ID0 Register */
#define bfin_read_CAN1_MB17_ID0()      bfin_read16(CAN1_MB17_ID0)
#define bfin_write_CAN1_MB17_ID0(val)  bfin_write16(CAN1_MB17_ID0, val)
#define pCAN1_MB17_ID1                 ((uint16_t volatile *)CAN1_MB17_ID1) /* CAN Controller 1 Mailbox 17 ID1 Register */
#define bfin_read_CAN1_MB17_ID1()      bfin_read16(CAN1_MB17_ID1)
#define bfin_write_CAN1_MB17_ID1(val)  bfin_write16(CAN1_MB17_ID1, val)
#define pCAN1_MB18_DATA0               ((uint16_t volatile *)CAN1_MB18_DATA0) /* CAN Controller 1 Mailbox 18 Data 0 Register */
#define bfin_read_CAN1_MB18_DATA0()    bfin_read16(CAN1_MB18_DATA0)
#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
#define pCAN1_MB18_DATA1               ((uint16_t volatile *)CAN1_MB18_DATA1) /* CAN Controller 1 Mailbox 18 Data 1 Register */
#define bfin_read_CAN1_MB18_DATA1()    bfin_read16(CAN1_MB18_DATA1)
#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
#define pCAN1_MB18_DATA2               ((uint16_t volatile *)CAN1_MB18_DATA2) /* CAN Controller 1 Mailbox 18 Data 2 Register */
#define bfin_read_CAN1_MB18_DATA2()    bfin_read16(CAN1_MB18_DATA2)
#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
#define pCAN1_MB18_DATA3               ((uint16_t volatile *)CAN1_MB18_DATA3) /* CAN Controller 1 Mailbox 18 Data 3 Register */
#define bfin_read_CAN1_MB18_DATA3()    bfin_read16(CAN1_MB18_DATA3)
#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
#define pCAN1_MB18_LENGTH              ((uint16_t volatile *)CAN1_MB18_LENGTH) /* CAN Controller 1 Mailbox 18 Length Register */
#define bfin_read_CAN1_MB18_LENGTH()   bfin_read16(CAN1_MB18_LENGTH)
#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
#define pCAN1_MB18_TIMESTAMP           ((uint16_t volatile *)CAN1_MB18_TIMESTAMP) /* CAN Controller 1 Mailbox 18 Timestamp Register */
#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
#define pCAN1_MB18_ID0                 ((uint16_t volatile *)CAN1_MB18_ID0) /* CAN Controller 1 Mailbox 18 ID0 Register */
#define bfin_read_CAN1_MB18_ID0()      bfin_read16(CAN1_MB18_ID0)
#define bfin_write_CAN1_MB18_ID0(val)  bfin_write16(CAN1_MB18_ID0, val)
#define pCAN1_MB18_ID1                 ((uint16_t volatile *)CAN1_MB18_ID1) /* CAN Controller 1 Mailbox 18 ID1 Register */
#define bfin_read_CAN1_MB18_ID1()      bfin_read16(CAN1_MB18_ID1)
#define bfin_write_CAN1_MB18_ID1(val)  bfin_write16(CAN1_MB18_ID1, val)
#define pCAN1_MB19_DATA0               ((uint16_t volatile *)CAN1_MB19_DATA0) /* CAN Controller 1 Mailbox 19 Data 0 Register */
#define bfin_read_CAN1_MB19_DATA0()    bfin_read16(CAN1_MB19_DATA0)
#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
#define pCAN1_MB19_DATA1               ((uint16_t volatile *)CAN1_MB19_DATA1) /* CAN Controller 1 Mailbox 19 Data 1 Register */
#define bfin_read_CAN1_MB19_DATA1()    bfin_read16(CAN1_MB19_DATA1)
#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
#define pCAN1_MB19_DATA2               ((uint16_t volatile *)CAN1_MB19_DATA2) /* CAN Controller 1 Mailbox 19 Data 2 Register */
#define bfin_read_CAN1_MB19_DATA2()    bfin_read16(CAN1_MB19_DATA2)
#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
#define pCAN1_MB19_DATA3               ((uint16_t volatile *)CAN1_MB19_DATA3) /* CAN Controller 1 Mailbox 19 Data 3 Register */
#define bfin_read_CAN1_MB19_DATA3()    bfin_read16(CAN1_MB19_DATA3)
#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
#define pCAN1_MB19_LENGTH              ((uint16_t volatile *)CAN1_MB19_LENGTH) /* CAN Controller 1 Mailbox 19 Length Register */
#define bfin_read_CAN1_MB19_LENGTH()   bfin_read16(CAN1_MB19_LENGTH)
#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
#define pCAN1_MB19_TIMESTAMP           ((uint16_t volatile *)CAN1_MB19_TIMESTAMP) /* CAN Controller 1 Mailbox 19 Timestamp Register */
#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
#define pCAN1_MB19_ID0                 ((uint16_t volatile *)CAN1_MB19_ID0) /* CAN Controller 1 Mailbox 19 ID0 Register */
#define bfin_read_CAN1_MB19_ID0()      bfin_read16(CAN1_MB19_ID0)
#define bfin_write_CAN1_MB19_ID0(val)  bfin_write16(CAN1_MB19_ID0, val)
#define pCAN1_MB19_ID1                 ((uint16_t volatile *)CAN1_MB19_ID1) /* CAN Controller 1 Mailbox 19 ID1 Register */
#define bfin_read_CAN1_MB19_ID1()      bfin_read16(CAN1_MB19_ID1)
#define bfin_write_CAN1_MB19_ID1(val)  bfin_write16(CAN1_MB19_ID1, val)
#define pCAN1_MB20_DATA0               ((uint16_t volatile *)CAN1_MB20_DATA0) /* CAN Controller 1 Mailbox 20 Data 0 Register */
#define bfin_read_CAN1_MB20_DATA0()    bfin_read16(CAN1_MB20_DATA0)
#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
#define pCAN1_MB20_DATA1               ((uint16_t volatile *)CAN1_MB20_DATA1) /* CAN Controller 1 Mailbox 20 Data 1 Register */
#define bfin_read_CAN1_MB20_DATA1()    bfin_read16(CAN1_MB20_DATA1)
#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
#define pCAN1_MB20_DATA2               ((uint16_t volatile *)CAN1_MB20_DATA2) /* CAN Controller 1 Mailbox 20 Data 2 Register */
#define bfin_read_CAN1_MB20_DATA2()    bfin_read16(CAN1_MB20_DATA2)
#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
#define pCAN1_MB20_DATA3               ((uint16_t volatile *)CAN1_MB20_DATA3) /* CAN Controller 1 Mailbox 20 Data 3 Register */
#define bfin_read_CAN1_MB20_DATA3()    bfin_read16(CAN1_MB20_DATA3)
#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
#define pCAN1_MB20_LENGTH              ((uint16_t volatile *)CAN1_MB20_LENGTH) /* CAN Controller 1 Mailbox 20 Length Register */
#define bfin_read_CAN1_MB20_LENGTH()   bfin_read16(CAN1_MB20_LENGTH)
#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
#define pCAN1_MB20_TIMESTAMP           ((uint16_t volatile *)CAN1_MB20_TIMESTAMP) /* CAN Controller 1 Mailbox 20 Timestamp Register */
#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
#define pCAN1_MB20_ID0                 ((uint16_t volatile *)CAN1_MB20_ID0) /* CAN Controller 1 Mailbox 20 ID0 Register */
#define bfin_read_CAN1_MB20_ID0()      bfin_read16(CAN1_MB20_ID0)
#define bfin_write_CAN1_MB20_ID0(val)  bfin_write16(CAN1_MB20_ID0, val)
#define pCAN1_MB20_ID1                 ((uint16_t volatile *)CAN1_MB20_ID1) /* CAN Controller 1 Mailbox 20 ID1 Register */
#define bfin_read_CAN1_MB20_ID1()      bfin_read16(CAN1_MB20_ID1)
#define bfin_write_CAN1_MB20_ID1(val)  bfin_write16(CAN1_MB20_ID1, val)
#define pCAN1_MB21_DATA0               ((uint16_t volatile *)CAN1_MB21_DATA0) /* CAN Controller 1 Mailbox 21 Data 0 Register */
#define bfin_read_CAN1_MB21_DATA0()    bfin_read16(CAN1_MB21_DATA0)
#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
#define pCAN1_MB21_DATA1               ((uint16_t volatile *)CAN1_MB21_DATA1) /* CAN Controller 1 Mailbox 21 Data 1 Register */
#define bfin_read_CAN1_MB21_DATA1()    bfin_read16(CAN1_MB21_DATA1)
#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
#define pCAN1_MB21_DATA2               ((uint16_t volatile *)CAN1_MB21_DATA2) /* CAN Controller 1 Mailbox 21 Data 2 Register */
#define bfin_read_CAN1_MB21_DATA2()    bfin_read16(CAN1_MB21_DATA2)
#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
#define pCAN1_MB21_DATA3               ((uint16_t volatile *)CAN1_MB21_DATA3) /* CAN Controller 1 Mailbox 21 Data 3 Register */
#define bfin_read_CAN1_MB21_DATA3()    bfin_read16(CAN1_MB21_DATA3)
#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
#define pCAN1_MB21_LENGTH              ((uint16_t volatile *)CAN1_MB21_LENGTH) /* CAN Controller 1 Mailbox 21 Length Register */
#define bfin_read_CAN1_MB21_LENGTH()   bfin_read16(CAN1_MB21_LENGTH)
#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
#define pCAN1_MB21_TIMESTAMP           ((uint16_t volatile *)CAN1_MB21_TIMESTAMP) /* CAN Controller 1 Mailbox 21 Timestamp Register */
#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
#define pCAN1_MB21_ID0                 ((uint16_t volatile *)CAN1_MB21_ID0) /* CAN Controller 1 Mailbox 21 ID0 Register */
#define bfin_read_CAN1_MB21_ID0()      bfin_read16(CAN1_MB21_ID0)
#define bfin_write_CAN1_MB21_ID0(val)  bfin_write16(CAN1_MB21_ID0, val)
#define pCAN1_MB21_ID1                 ((uint16_t volatile *)CAN1_MB21_ID1) /* CAN Controller 1 Mailbox 21 ID1 Register */
#define bfin_read_CAN1_MB21_ID1()      bfin_read16(CAN1_MB21_ID1)
#define bfin_write_CAN1_MB21_ID1(val)  bfin_write16(CAN1_MB21_ID1, val)
#define pCAN1_MB22_DATA0               ((uint16_t volatile *)CAN1_MB22_DATA0) /* CAN Controller 1 Mailbox 22 Data 0 Register */
#define bfin_read_CAN1_MB22_DATA0()    bfin_read16(CAN1_MB22_DATA0)
#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
#define pCAN1_MB22_DATA1               ((uint16_t volatile *)CAN1_MB22_DATA1) /* CAN Controller 1 Mailbox 22 Data 1 Register */
#define bfin_read_CAN1_MB22_DATA1()    bfin_read16(CAN1_MB22_DATA1)
#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
#define pCAN1_MB22_DATA2               ((uint16_t volatile *)CAN1_MB22_DATA2) /* CAN Controller 1 Mailbox 22 Data 2 Register */
#define bfin_read_CAN1_MB22_DATA2()    bfin_read16(CAN1_MB22_DATA2)
#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
#define pCAN1_MB22_DATA3               ((uint16_t volatile *)CAN1_MB22_DATA3) /* CAN Controller 1 Mailbox 22 Data 3 Register */
#define bfin_read_CAN1_MB22_DATA3()    bfin_read16(CAN1_MB22_DATA3)
#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
#define pCAN1_MB22_LENGTH              ((uint16_t volatile *)CAN1_MB22_LENGTH) /* CAN Controller 1 Mailbox 22 Length Register */
#define bfin_read_CAN1_MB22_LENGTH()   bfin_read16(CAN1_MB22_LENGTH)
#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
#define pCAN1_MB22_TIMESTAMP           ((uint16_t volatile *)CAN1_MB22_TIMESTAMP) /* CAN Controller 1 Mailbox 22 Timestamp Register */
#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
#define pCAN1_MB22_ID0                 ((uint16_t volatile *)CAN1_MB22_ID0) /* CAN Controller 1 Mailbox 22 ID0 Register */
#define bfin_read_CAN1_MB22_ID0()      bfin_read16(CAN1_MB22_ID0)
#define bfin_write_CAN1_MB22_ID0(val)  bfin_write16(CAN1_MB22_ID0, val)
#define pCAN1_MB22_ID1                 ((uint16_t volatile *)CAN1_MB22_ID1) /* CAN Controller 1 Mailbox 22 ID1 Register */
#define bfin_read_CAN1_MB22_ID1()      bfin_read16(CAN1_MB22_ID1)
#define bfin_write_CAN1_MB22_ID1(val)  bfin_write16(CAN1_MB22_ID1, val)
#define pCAN1_MB23_DATA0               ((uint16_t volatile *)CAN1_MB23_DATA0) /* CAN Controller 1 Mailbox 23 Data 0 Register */
#define bfin_read_CAN1_MB23_DATA0()    bfin_read16(CAN1_MB23_DATA0)
#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
#define pCAN1_MB23_DATA1               ((uint16_t volatile *)CAN1_MB23_DATA1) /* CAN Controller 1 Mailbox 23 Data 1 Register */
#define bfin_read_CAN1_MB23_DATA1()    bfin_read16(CAN1_MB23_DATA1)
#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
#define pCAN1_MB23_DATA2               ((uint16_t volatile *)CAN1_MB23_DATA2) /* CAN Controller 1 Mailbox 23 Data 2 Register */
#define bfin_read_CAN1_MB23_DATA2()    bfin_read16(CAN1_MB23_DATA2)
#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
#define pCAN1_MB23_DATA3               ((uint16_t volatile *)CAN1_MB23_DATA3) /* CAN Controller 1 Mailbox 23 Data 3 Register */
#define bfin_read_CAN1_MB23_DATA3()    bfin_read16(CAN1_MB23_DATA3)
#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
#define pCAN1_MB23_LENGTH              ((uint16_t volatile *)CAN1_MB23_LENGTH) /* CAN Controller 1 Mailbox 23 Length Register */
#define bfin_read_CAN1_MB23_LENGTH()   bfin_read16(CAN1_MB23_LENGTH)
#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
#define pCAN1_MB23_TIMESTAMP           ((uint16_t volatile *)CAN1_MB23_TIMESTAMP) /* CAN Controller 1 Mailbox 23 Timestamp Register */
#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
#define pCAN1_MB23_ID0                 ((uint16_t volatile *)CAN1_MB23_ID0) /* CAN Controller 1 Mailbox 23 ID0 Register */
#define bfin_read_CAN1_MB23_ID0()      bfin_read16(CAN1_MB23_ID0)
#define bfin_write_CAN1_MB23_ID0(val)  bfin_write16(CAN1_MB23_ID0, val)
#define pCAN1_MB23_ID1                 ((uint16_t volatile *)CAN1_MB23_ID1) /* CAN Controller 1 Mailbox 23 ID1 Register */
#define bfin_read_CAN1_MB23_ID1()      bfin_read16(CAN1_MB23_ID1)
#define bfin_write_CAN1_MB23_ID1(val)  bfin_write16(CAN1_MB23_ID1, val)
#define pCAN1_MB24_DATA0               ((uint16_t volatile *)CAN1_MB24_DATA0) /* CAN Controller 1 Mailbox 24 Data 0 Register */
#define bfin_read_CAN1_MB24_DATA0()    bfin_read16(CAN1_MB24_DATA0)
#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
#define pCAN1_MB24_DATA1               ((uint16_t volatile *)CAN1_MB24_DATA1) /* CAN Controller 1 Mailbox 24 Data 1 Register */
#define bfin_read_CAN1_MB24_DATA1()    bfin_read16(CAN1_MB24_DATA1)
#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
#define pCAN1_MB24_DATA2               ((uint16_t volatile *)CAN1_MB24_DATA2) /* CAN Controller 1 Mailbox 24 Data 2 Register */
#define bfin_read_CAN1_MB24_DATA2()    bfin_read16(CAN1_MB24_DATA2)
#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
#define pCAN1_MB24_DATA3               ((uint16_t volatile *)CAN1_MB24_DATA3) /* CAN Controller 1 Mailbox 24 Data 3 Register */
#define bfin_read_CAN1_MB24_DATA3()    bfin_read16(CAN1_MB24_DATA3)
#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
#define pCAN1_MB24_LENGTH              ((uint16_t volatile *)CAN1_MB24_LENGTH) /* CAN Controller 1 Mailbox 24 Length Register */
#define bfin_read_CAN1_MB24_LENGTH()   bfin_read16(CAN1_MB24_LENGTH)
#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
#define pCAN1_MB24_TIMESTAMP           ((uint16_t volatile *)CAN1_MB24_TIMESTAMP) /* CAN Controller 1 Mailbox 24 Timestamp Register */
#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
#define pCAN1_MB24_ID0                 ((uint16_t volatile *)CAN1_MB24_ID0) /* CAN Controller 1 Mailbox 24 ID0 Register */
#define bfin_read_CAN1_MB24_ID0()      bfin_read16(CAN1_MB24_ID0)
#define bfin_write_CAN1_MB24_ID0(val)  bfin_write16(CAN1_MB24_ID0, val)
#define pCAN1_MB24_ID1                 ((uint16_t volatile *)CAN1_MB24_ID1) /* CAN Controller 1 Mailbox 24 ID1 Register */
#define bfin_read_CAN1_MB24_ID1()      bfin_read16(CAN1_MB24_ID1)
#define bfin_write_CAN1_MB24_ID1(val)  bfin_write16(CAN1_MB24_ID1, val)
#define pCAN1_MB25_DATA0               ((uint16_t volatile *)CAN1_MB25_DATA0) /* CAN Controller 1 Mailbox 25 Data 0 Register */
#define bfin_read_CAN1_MB25_DATA0()    bfin_read16(CAN1_MB25_DATA0)
#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
#define pCAN1_MB25_DATA1               ((uint16_t volatile *)CAN1_MB25_DATA1) /* CAN Controller 1 Mailbox 25 Data 1 Register */
#define bfin_read_CAN1_MB25_DATA1()    bfin_read16(CAN1_MB25_DATA1)
#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
#define pCAN1_MB25_DATA2               ((uint16_t volatile *)CAN1_MB25_DATA2) /* CAN Controller 1 Mailbox 25 Data 2 Register */
#define bfin_read_CAN1_MB25_DATA2()    bfin_read16(CAN1_MB25_DATA2)
#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
#define pCAN1_MB25_DATA3               ((uint16_t volatile *)CAN1_MB25_DATA3) /* CAN Controller 1 Mailbox 25 Data 3 Register */
#define bfin_read_CAN1_MB25_DATA3()    bfin_read16(CAN1_MB25_DATA3)
#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
#define pCAN1_MB25_LENGTH              ((uint16_t volatile *)CAN1_MB25_LENGTH) /* CAN Controller 1 Mailbox 25 Length Register */
#define bfin_read_CAN1_MB25_LENGTH()   bfin_read16(CAN1_MB25_LENGTH)
#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
#define pCAN1_MB25_TIMESTAMP           ((uint16_t volatile *)CAN1_MB25_TIMESTAMP) /* CAN Controller 1 Mailbox 25 Timestamp Register */
#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
#define pCAN1_MB25_ID0                 ((uint16_t volatile *)CAN1_MB25_ID0) /* CAN Controller 1 Mailbox 25 ID0 Register */
#define bfin_read_CAN1_MB25_ID0()      bfin_read16(CAN1_MB25_ID0)
#define bfin_write_CAN1_MB25_ID0(val)  bfin_write16(CAN1_MB25_ID0, val)
#define pCAN1_MB25_ID1                 ((uint16_t volatile *)CAN1_MB25_ID1) /* CAN Controller 1 Mailbox 25 ID1 Register */
#define bfin_read_CAN1_MB25_ID1()      bfin_read16(CAN1_MB25_ID1)
#define bfin_write_CAN1_MB25_ID1(val)  bfin_write16(CAN1_MB25_ID1, val)
#define pCAN1_MB26_DATA0               ((uint16_t volatile *)CAN1_MB26_DATA0) /* CAN Controller 1 Mailbox 26 Data 0 Register */
#define bfin_read_CAN1_MB26_DATA0()    bfin_read16(CAN1_MB26_DATA0)
#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
#define pCAN1_MB26_DATA1               ((uint16_t volatile *)CAN1_MB26_DATA1) /* CAN Controller 1 Mailbox 26 Data 1 Register */
#define bfin_read_CAN1_MB26_DATA1()    bfin_read16(CAN1_MB26_DATA1)
#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
#define pCAN1_MB26_DATA2               ((uint16_t volatile *)CAN1_MB26_DATA2) /* CAN Controller 1 Mailbox 26 Data 2 Register */
#define bfin_read_CAN1_MB26_DATA2()    bfin_read16(CAN1_MB26_DATA2)
#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
#define pCAN1_MB26_DATA3               ((uint16_t volatile *)CAN1_MB26_DATA3) /* CAN Controller 1 Mailbox 26 Data 3 Register */
#define bfin_read_CAN1_MB26_DATA3()    bfin_read16(CAN1_MB26_DATA3)
#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
#define pCAN1_MB26_LENGTH              ((uint16_t volatile *)CAN1_MB26_LENGTH) /* CAN Controller 1 Mailbox 26 Length Register */
#define bfin_read_CAN1_MB26_LENGTH()   bfin_read16(CAN1_MB26_LENGTH)
#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
#define pCAN1_MB26_TIMESTAMP           ((uint16_t volatile *)CAN1_MB26_TIMESTAMP) /* CAN Controller 1 Mailbox 26 Timestamp Register */
#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
#define pCAN1_MB26_ID0                 ((uint16_t volatile *)CAN1_MB26_ID0) /* CAN Controller 1 Mailbox 26 ID0 Register */
#define bfin_read_CAN1_MB26_ID0()      bfin_read16(CAN1_MB26_ID0)
#define bfin_write_CAN1_MB26_ID0(val)  bfin_write16(CAN1_MB26_ID0, val)
#define pCAN1_MB26_ID1                 ((uint16_t volatile *)CAN1_MB26_ID1) /* CAN Controller 1 Mailbox 26 ID1 Register */
#define bfin_read_CAN1_MB26_ID1()      bfin_read16(CAN1_MB26_ID1)
#define bfin_write_CAN1_MB26_ID1(val)  bfin_write16(CAN1_MB26_ID1, val)
#define pCAN1_MB27_DATA0               ((uint16_t volatile *)CAN1_MB27_DATA0) /* CAN Controller 1 Mailbox 27 Data 0 Register */
#define bfin_read_CAN1_MB27_DATA0()    bfin_read16(CAN1_MB27_DATA0)
#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
#define pCAN1_MB27_DATA1               ((uint16_t volatile *)CAN1_MB27_DATA1) /* CAN Controller 1 Mailbox 27 Data 1 Register */
#define bfin_read_CAN1_MB27_DATA1()    bfin_read16(CAN1_MB27_DATA1)
#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
#define pCAN1_MB27_DATA2               ((uint16_t volatile *)CAN1_MB27_DATA2) /* CAN Controller 1 Mailbox 27 Data 2 Register */
#define bfin_read_CAN1_MB27_DATA2()    bfin_read16(CAN1_MB27_DATA2)
#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
#define pCAN1_MB27_DATA3               ((uint16_t volatile *)CAN1_MB27_DATA3) /* CAN Controller 1 Mailbox 27 Data 3 Register */
#define bfin_read_CAN1_MB27_DATA3()    bfin_read16(CAN1_MB27_DATA3)
#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
#define pCAN1_MB27_LENGTH              ((uint16_t volatile *)CAN1_MB27_LENGTH) /* CAN Controller 1 Mailbox 27 Length Register */
#define bfin_read_CAN1_MB27_LENGTH()   bfin_read16(CAN1_MB27_LENGTH)
#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
#define pCAN1_MB27_TIMESTAMP           ((uint16_t volatile *)CAN1_MB27_TIMESTAMP) /* CAN Controller 1 Mailbox 27 Timestamp Register */
#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
#define pCAN1_MB27_ID0                 ((uint16_t volatile *)CAN1_MB27_ID0) /* CAN Controller 1 Mailbox 27 ID0 Register */
#define bfin_read_CAN1_MB27_ID0()      bfin_read16(CAN1_MB27_ID0)
#define bfin_write_CAN1_MB27_ID0(val)  bfin_write16(CAN1_MB27_ID0, val)
#define pCAN1_MB27_ID1                 ((uint16_t volatile *)CAN1_MB27_ID1) /* CAN Controller 1 Mailbox 27 ID1 Register */
#define bfin_read_CAN1_MB27_ID1()      bfin_read16(CAN1_MB27_ID1)
#define bfin_write_CAN1_MB27_ID1(val)  bfin_write16(CAN1_MB27_ID1, val)
#define pCAN1_MB28_DATA0               ((uint16_t volatile *)CAN1_MB28_DATA0) /* CAN Controller 1 Mailbox 28 Data 0 Register */
#define bfin_read_CAN1_MB28_DATA0()    bfin_read16(CAN1_MB28_DATA0)
#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
#define pCAN1_MB28_DATA1               ((uint16_t volatile *)CAN1_MB28_DATA1) /* CAN Controller 1 Mailbox 28 Data 1 Register */
#define bfin_read_CAN1_MB28_DATA1()    bfin_read16(CAN1_MB28_DATA1)
#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
#define pCAN1_MB28_DATA2               ((uint16_t volatile *)CAN1_MB28_DATA2) /* CAN Controller 1 Mailbox 28 Data 2 Register */
#define bfin_read_CAN1_MB28_DATA2()    bfin_read16(CAN1_MB28_DATA2)
#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
#define pCAN1_MB28_DATA3               ((uint16_t volatile *)CAN1_MB28_DATA3) /* CAN Controller 1 Mailbox 28 Data 3 Register */
#define bfin_read_CAN1_MB28_DATA3()    bfin_read16(CAN1_MB28_DATA3)
#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
#define pCAN1_MB28_LENGTH              ((uint16_t volatile *)CAN1_MB28_LENGTH) /* CAN Controller 1 Mailbox 28 Length Register */
#define bfin_read_CAN1_MB28_LENGTH()   bfin_read16(CAN1_MB28_LENGTH)
#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
#define pCAN1_MB28_TIMESTAMP           ((uint16_t volatile *)CAN1_MB28_TIMESTAMP) /* CAN Controller 1 Mailbox 28 Timestamp Register */
#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
#define pCAN1_MB28_ID0                 ((uint16_t volatile *)CAN1_MB28_ID0) /* CAN Controller 1 Mailbox 28 ID0 Register */
#define bfin_read_CAN1_MB28_ID0()      bfin_read16(CAN1_MB28_ID0)
#define bfin_write_CAN1_MB28_ID0(val)  bfin_write16(CAN1_MB28_ID0, val)
#define pCAN1_MB28_ID1                 ((uint16_t volatile *)CAN1_MB28_ID1) /* CAN Controller 1 Mailbox 28 ID1 Register */
#define bfin_read_CAN1_MB28_ID1()      bfin_read16(CAN1_MB28_ID1)
#define bfin_write_CAN1_MB28_ID1(val)  bfin_write16(CAN1_MB28_ID1, val)
#define pCAN1_MB29_DATA0               ((uint16_t volatile *)CAN1_MB29_DATA0) /* CAN Controller 1 Mailbox 29 Data 0 Register */
#define bfin_read_CAN1_MB29_DATA0()    bfin_read16(CAN1_MB29_DATA0)
#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
#define pCAN1_MB29_DATA1               ((uint16_t volatile *)CAN1_MB29_DATA1) /* CAN Controller 1 Mailbox 29 Data 1 Register */
#define bfin_read_CAN1_MB29_DATA1()    bfin_read16(CAN1_MB29_DATA1)
#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
#define pCAN1_MB29_DATA2               ((uint16_t volatile *)CAN1_MB29_DATA2) /* CAN Controller 1 Mailbox 29 Data 2 Register */
#define bfin_read_CAN1_MB29_DATA2()    bfin_read16(CAN1_MB29_DATA2)
#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
#define pCAN1_MB29_DATA3               ((uint16_t volatile *)CAN1_MB29_DATA3) /* CAN Controller 1 Mailbox 29 Data 3 Register */
#define bfin_read_CAN1_MB29_DATA3()    bfin_read16(CAN1_MB29_DATA3)
#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
#define pCAN1_MB29_LENGTH              ((uint16_t volatile *)CAN1_MB29_LENGTH) /* CAN Controller 1 Mailbox 29 Length Register */
#define bfin_read_CAN1_MB29_LENGTH()   bfin_read16(CAN1_MB29_LENGTH)
#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
#define pCAN1_MB29_TIMESTAMP           ((uint16_t volatile *)CAN1_MB29_TIMESTAMP) /* CAN Controller 1 Mailbox 29 Timestamp Register */
#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
#define pCAN1_MB29_ID0                 ((uint16_t volatile *)CAN1_MB29_ID0) /* CAN Controller 1 Mailbox 29 ID0 Register */
#define bfin_read_CAN1_MB29_ID0()      bfin_read16(CAN1_MB29_ID0)
#define bfin_write_CAN1_MB29_ID0(val)  bfin_write16(CAN1_MB29_ID0, val)
#define pCAN1_MB29_ID1                 ((uint16_t volatile *)CAN1_MB29_ID1) /* CAN Controller 1 Mailbox 29 ID1 Register */
#define bfin_read_CAN1_MB29_ID1()      bfin_read16(CAN1_MB29_ID1)
#define bfin_write_CAN1_MB29_ID1(val)  bfin_write16(CAN1_MB29_ID1, val)
#define pCAN1_MB30_DATA0               ((uint16_t volatile *)CAN1_MB30_DATA0) /* CAN Controller 1 Mailbox 30 Data 0 Register */
#define bfin_read_CAN1_MB30_DATA0()    bfin_read16(CAN1_MB30_DATA0)
#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
#define pCAN1_MB30_DATA1               ((uint16_t volatile *)CAN1_MB30_DATA1) /* CAN Controller 1 Mailbox 30 Data 1 Register */
#define bfin_read_CAN1_MB30_DATA1()    bfin_read16(CAN1_MB30_DATA1)
#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
#define pCAN1_MB30_DATA2               ((uint16_t volatile *)CAN1_MB30_DATA2) /* CAN Controller 1 Mailbox 30 Data 2 Register */
#define bfin_read_CAN1_MB30_DATA2()    bfin_read16(CAN1_MB30_DATA2)
#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
#define pCAN1_MB30_DATA3               ((uint16_t volatile *)CAN1_MB30_DATA3) /* CAN Controller 1 Mailbox 30 Data 3 Register */
#define bfin_read_CAN1_MB30_DATA3()    bfin_read16(CAN1_MB30_DATA3)
#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
#define pCAN1_MB30_LENGTH              ((uint16_t volatile *)CAN1_MB30_LENGTH) /* CAN Controller 1 Mailbox 30 Length Register */
#define bfin_read_CAN1_MB30_LENGTH()   bfin_read16(CAN1_MB30_LENGTH)
#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
#define pCAN1_MB30_TIMESTAMP           ((uint16_t volatile *)CAN1_MB30_TIMESTAMP) /* CAN Controller 1 Mailbox 30 Timestamp Register */
#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
#define pCAN1_MB30_ID0                 ((uint16_t volatile *)CAN1_MB30_ID0) /* CAN Controller 1 Mailbox 30 ID0 Register */
#define bfin_read_CAN1_MB30_ID0()      bfin_read16(CAN1_MB30_ID0)
#define bfin_write_CAN1_MB30_ID0(val)  bfin_write16(CAN1_MB30_ID0, val)
#define pCAN1_MB30_ID1                 ((uint16_t volatile *)CAN1_MB30_ID1) /* CAN Controller 1 Mailbox 30 ID1 Register */
#define bfin_read_CAN1_MB30_ID1()      bfin_read16(CAN1_MB30_ID1)
#define bfin_write_CAN1_MB30_ID1(val)  bfin_write16(CAN1_MB30_ID1, val)
#define pCAN1_MB31_DATA0               ((uint16_t volatile *)CAN1_MB31_DATA0) /* CAN Controller 1 Mailbox 31 Data 0 Register */
#define bfin_read_CAN1_MB31_DATA0()    bfin_read16(CAN1_MB31_DATA0)
#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
#define pCAN1_MB31_DATA1               ((uint16_t volatile *)CAN1_MB31_DATA1) /* CAN Controller 1 Mailbox 31 Data 1 Register */
#define bfin_read_CAN1_MB31_DATA1()    bfin_read16(CAN1_MB31_DATA1)
#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
#define pCAN1_MB31_DATA2               ((uint16_t volatile *)CAN1_MB31_DATA2) /* CAN Controller 1 Mailbox 31 Data 2 Register */
#define bfin_read_CAN1_MB31_DATA2()    bfin_read16(CAN1_MB31_DATA2)
#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
#define pCAN1_MB31_DATA3               ((uint16_t volatile *)CAN1_MB31_DATA3) /* CAN Controller 1 Mailbox 31 Data 3 Register */
#define bfin_read_CAN1_MB31_DATA3()    bfin_read16(CAN1_MB31_DATA3)
#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
#define pCAN1_MB31_LENGTH              ((uint16_t volatile *)CAN1_MB31_LENGTH) /* CAN Controller 1 Mailbox 31 Length Register */
#define bfin_read_CAN1_MB31_LENGTH()   bfin_read16(CAN1_MB31_LENGTH)
#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
#define pCAN1_MB31_TIMESTAMP           ((uint16_t volatile *)CAN1_MB31_TIMESTAMP) /* CAN Controller 1 Mailbox 31 Timestamp Register */
#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
#define pCAN1_MB31_ID0                 ((uint16_t volatile *)CAN1_MB31_ID0) /* CAN Controller 1 Mailbox 31 ID0 Register */
#define bfin_read_CAN1_MB31_ID0()      bfin_read16(CAN1_MB31_ID0)
#define bfin_write_CAN1_MB31_ID0(val)  bfin_write16(CAN1_MB31_ID0, val)
#define pCAN1_MB31_ID1                 ((uint16_t volatile *)CAN1_MB31_ID1) /* CAN Controller 1 Mailbox 31 ID1 Register */
#define bfin_read_CAN1_MB31_ID1()      bfin_read16(CAN1_MB31_ID1)
#define bfin_write_CAN1_MB31_ID1(val)  bfin_write16(CAN1_MB31_ID1, val)
#define pSPI0_CTL                      ((uint16_t volatile *)SPI0_CTL) /* SPI0 Control Register */
#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
#define pSPI0_FLG                      ((uint16_t volatile *)SPI0_FLG) /* SPI0 Flag Register */
#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
#define pSPI0_STAT                     ((uint16_t volatile *)SPI0_STAT) /* SPI0 Status Register */
#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
#define pSPI0_TDBR                     ((uint16_t volatile *)SPI0_TDBR) /* SPI0 Transmit Data Buffer Register */
#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
#define pSPI0_RDBR                     ((uint16_t volatile *)SPI0_RDBR) /* SPI0 Receive Data Buffer Register */
#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
#define pSPI0_BAUD                     ((uint16_t volatile *)SPI0_BAUD) /* SPI0 Baud Rate Register */
#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
#define pSPI0_SHADOW                   ((uint16_t volatile *)SPI0_SHADOW) /* SPI0 Receive Data Buffer Shadow Register */
#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
#define pSPI1_CTL                      ((uint16_t volatile *)SPI1_CTL) /* SPI1 Control Register */
#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
#define pSPI1_FLG                      ((uint16_t volatile *)SPI1_FLG) /* SPI1 Flag Register */
#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
#define pSPI1_STAT                     ((uint16_t volatile *)SPI1_STAT) /* SPI1 Status Register */
#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
#define pSPI1_TDBR                     ((uint16_t volatile *)SPI1_TDBR) /* SPI1 Transmit Data Buffer Register */
#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
#define pSPI1_RDBR                     ((uint16_t volatile *)SPI1_RDBR) /* SPI1 Receive Data Buffer Register */
#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
#define pSPI1_BAUD                     ((uint16_t volatile *)SPI1_BAUD) /* SPI1 Baud Rate Register */
#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
#define pSPI1_SHADOW                   ((uint16_t volatile *)SPI1_SHADOW) /* SPI1 Receive Data Buffer Shadow Register */
#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
#define pTWI0_CLKDIV                   ((uint16_t volatile *)TWI0_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI0_CLKDIV()        bfin_read16(TWI0_CLKDIV)
#define bfin_write_TWI0_CLKDIV(val)    bfin_write16(TWI0_CLKDIV, val)
#define pTWI0_CONTROL                  ((uint16_t volatile *)TWI0_CONTROL) /* TWI Control Register */
#define bfin_read_TWI0_CONTROL()       bfin_read16(TWI0_CONTROL)
#define bfin_write_TWI0_CONTROL(val)   bfin_write16(TWI0_CONTROL, val)
#define pTWI0_SLAVE_CTL                ((uint16_t volatile *)TWI0_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI0_SLAVE_CTL()     bfin_read16(TWI0_SLAVE_CTL)
#define bfin_write_TWI0_SLAVE_CTL(val) bfin_write16(TWI0_SLAVE_CTL, val)
#define pTWI0_SLAVE_STAT               ((uint16_t volatile *)TWI0_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI0_SLAVE_STAT()    bfin_read16(TWI0_SLAVE_STAT)
#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
#define pTWI0_SLAVE_ADDR               ((uint16_t volatile *)TWI0_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI0_SLAVE_ADDR()    bfin_read16(TWI0_SLAVE_ADDR)
#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
#define pTWI0_MASTER_CTL               ((uint16_t volatile *)TWI0_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI0_MASTER_CTL()    bfin_read16(TWI0_MASTER_CTL)
#define bfin_write_TWI0_MASTER_CTL(val) bfin_write16(TWI0_MASTER_CTL, val)
#define pTWI0_MASTER_STAT              ((uint16_t volatile *)TWI0_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI0_MASTER_STAT()   bfin_read16(TWI0_MASTER_STAT)
#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
#define pTWI0_MASTER_ADDR              ((uint16_t volatile *)TWI0_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI0_MASTER_ADDR()   bfin_read16(TWI0_MASTER_ADDR)
#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
#define pTWI0_INT_STAT                 ((uint16_t volatile *)TWI0_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI0_INT_STAT()      bfin_read16(TWI0_INT_STAT)
#define bfin_write_TWI0_INT_STAT(val)  bfin_write16(TWI0_INT_STAT, val)
#define pTWI0_INT_MASK                 ((uint16_t volatile *)TWI0_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI0_INT_MASK()      bfin_read16(TWI0_INT_MASK)
#define bfin_write_TWI0_INT_MASK(val)  bfin_write16(TWI0_INT_MASK, val)
#define pTWI0_FIFO_CTL                 ((uint16_t volatile *)TWI0_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI0_FIFO_CTL()      bfin_read16(TWI0_FIFO_CTL)
#define bfin_write_TWI0_FIFO_CTL(val)  bfin_write16(TWI0_FIFO_CTL, val)
#define pTWI0_FIFO_STAT                ((uint16_t volatile *)TWI0_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI0_FIFO_STAT()     bfin_read16(TWI0_FIFO_STAT)
#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
#define pTWI0_XMT_DATA8                ((uint16_t volatile *)TWI0_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI0_XMT_DATA8()     bfin_read16(TWI0_XMT_DATA8)
#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
#define pTWI0_XMT_DATA16               ((uint16_t volatile *)TWI0_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI0_XMT_DATA16()    bfin_read16(TWI0_XMT_DATA16)
#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
#define pTWI0_RCV_DATA8                ((uint16_t volatile *)TWI0_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI0_RCV_DATA8()     bfin_read16(TWI0_RCV_DATA8)
#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
#define pTWI0_RCV_DATA16               ((uint16_t volatile *)TWI0_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI0_RCV_DATA16()    bfin_read16(TWI0_RCV_DATA16)
#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
#define pTWI1_CLKDIV                   ((uint16_t volatile *)TWI1_CLKDIV) /* Clock Divider Register */
#define bfin_read_TWI1_CLKDIV()        bfin_read16(TWI1_CLKDIV)
#define bfin_write_TWI1_CLKDIV(val)    bfin_write16(TWI1_CLKDIV, val)
#define pTWI1_CONTROL                  ((uint16_t volatile *)TWI1_CONTROL) /* TWI Control Register */
#define bfin_read_TWI1_CONTROL()       bfin_read16(TWI1_CONTROL)
#define bfin_write_TWI1_CONTROL(val)   bfin_write16(TWI1_CONTROL, val)
#define pTWI1_SLAVE_CTL                ((uint16_t volatile *)TWI1_SLAVE_CTL) /* TWI Slave Mode Control Register */
#define bfin_read_TWI1_SLAVE_CTL()     bfin_read16(TWI1_SLAVE_CTL)
#define bfin_write_TWI1_SLAVE_CTL(val) bfin_write16(TWI1_SLAVE_CTL, val)
#define pTWI1_SLAVE_STAT               ((uint16_t volatile *)TWI1_SLAVE_STAT) /* TWI Slave Mode Status Register */
#define bfin_read_TWI1_SLAVE_STAT()    bfin_read16(TWI1_SLAVE_STAT)
#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
#define pTWI1_SLAVE_ADDR               ((uint16_t volatile *)TWI1_SLAVE_ADDR) /* TWI Slave Mode Address Register */
#define bfin_read_TWI1_SLAVE_ADDR()    bfin_read16(TWI1_SLAVE_ADDR)
#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
#define pTWI1_MASTER_CTL               ((uint16_t volatile *)TWI1_MASTER_CTL) /* TWI Master Mode Control Register */
#define bfin_read_TWI1_MASTER_CTL()    bfin_read16(TWI1_MASTER_CTL)
#define bfin_write_TWI1_MASTER_CTL(val) bfin_write16(TWI1_MASTER_CTL, val)
#define pTWI1_MASTER_STAT              ((uint16_t volatile *)TWI1_MASTER_STAT) /* TWI Master Mode Status Register */
#define bfin_read_TWI1_MASTER_STAT()   bfin_read16(TWI1_MASTER_STAT)
#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
#define pTWI1_MASTER_ADDR              ((uint16_t volatile *)TWI1_MASTER_ADDR) /* TWI Master Mode Address Register */
#define bfin_read_TWI1_MASTER_ADDR()   bfin_read16(TWI1_MASTER_ADDR)
#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
#define pTWI1_INT_STAT                 ((uint16_t volatile *)TWI1_INT_STAT) /* TWI Interrupt Status Register */
#define bfin_read_TWI1_INT_STAT()      bfin_read16(TWI1_INT_STAT)
#define bfin_write_TWI1_INT_STAT(val)  bfin_write16(TWI1_INT_STAT, val)
#define pTWI1_INT_MASK                 ((uint16_t volatile *)TWI1_INT_MASK) /* TWI Interrupt Mask Register */
#define bfin_read_TWI1_INT_MASK()      bfin_read16(TWI1_INT_MASK)
#define bfin_write_TWI1_INT_MASK(val)  bfin_write16(TWI1_INT_MASK, val)
#define pTWI1_FIFO_CTL                 ((uint16_t volatile *)TWI1_FIFO_CTL) /* TWI FIFO Control Register */
#define bfin_read_TWI1_FIFO_CTL()      bfin_read16(TWI1_FIFO_CTL)
#define bfin_write_TWI1_FIFO_CTL(val)  bfin_write16(TWI1_FIFO_CTL, val)
#define pTWI1_FIFO_STAT                ((uint16_t volatile *)TWI1_FIFO_STAT) /* TWI FIFO Status Register */
#define bfin_read_TWI1_FIFO_STAT()     bfin_read16(TWI1_FIFO_STAT)
#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
#define pTWI1_XMT_DATA8                ((uint16_t volatile *)TWI1_XMT_DATA8) /* TWI FIFO Transmit Data Single Byte Register */
#define bfin_read_TWI1_XMT_DATA8()     bfin_read16(TWI1_XMT_DATA8)
#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
#define pTWI1_XMT_DATA16               ((uint16_t volatile *)TWI1_XMT_DATA16) /* TWI FIFO Transmit Data Double Byte Register */
#define bfin_read_TWI1_XMT_DATA16()    bfin_read16(TWI1_XMT_DATA16)
#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
#define pTWI1_RCV_DATA8                ((uint16_t volatile *)TWI1_RCV_DATA8) /* TWI FIFO Receive Data Single Byte Register */
#define bfin_read_TWI1_RCV_DATA8()     bfin_read16(TWI1_RCV_DATA8)
#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
#define pTWI1_RCV_DATA16               ((uint16_t volatile *)TWI1_RCV_DATA16) /* TWI FIFO Receive Data Double Byte Register */
#define bfin_read_TWI1_RCV_DATA16()    bfin_read16(TWI1_RCV_DATA16)
#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
#define pSPORT1_TCR1                   ((uint16_t volatile *)SPORT1_TCR1) /* SPORT1 Transmit Configuration 1 Register */
#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
#define pSPORT1_TCR2                   ((uint16_t volatile *)SPORT1_TCR2) /* SPORT1 Transmit Configuration 2 Register */
#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
#define pSPORT1_TCLKDIV                ((uint16_t volatile *)SPORT1_TCLKDIV) /* SPORT1 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
#define pSPORT1_TFSDIV                 ((uint16_t volatile *)SPORT1_TFSDIV) /* SPORT1 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
#define pSPORT1_TX                     ((uint32_t volatile *)SPORT1_TX) /* SPORT1 Transmit Data Register */
#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
#define pSPORT1_RCR1                   ((uint16_t volatile *)SPORT1_RCR1) /* SPORT1 Receive Configuration 1 Register */
#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
#define pSPORT1_RCR2                   ((uint16_t volatile *)SPORT1_RCR2) /* SPORT1 Receive Configuration 2 Register */
#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
#define pSPORT1_RCLKDIV                ((uint16_t volatile *)SPORT1_RCLKDIV) /* SPORT1 Receive Serial Clock Divider Register */
#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
#define pSPORT1_RFSDIV                 ((uint16_t volatile *)SPORT1_RFSDIV) /* SPORT1 Receive Frame Sync Divider Register */
#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
#define pSPORT1_RX                     ((uint32_t volatile *)SPORT1_RX) /* SPORT1 Receive Data Register */
#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
#define pSPORT1_STAT                   ((uint16_t volatile *)SPORT1_STAT) /* SPORT1 Status Register */
#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
#define pSPORT1_MCMC1                  ((uint16_t volatile *)SPORT1_MCMC1) /* SPORT1 Multi channel Configuration Register 1 */
#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
#define pSPORT1_MCMC2                  ((uint16_t volatile *)SPORT1_MCMC2) /* SPORT1 Multi channel Configuration Register 2 */
#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
#define pSPORT1_CHNL                   ((uint16_t volatile *)SPORT1_CHNL) /* SPORT1 Current Channel Register */
#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
#define pSPORT1_MRCS0                  ((uint32_t volatile *)SPORT1_MRCS0) /* SPORT1 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
#define pSPORT1_MRCS1                  ((uint32_t volatile *)SPORT1_MRCS1) /* SPORT1 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
#define pSPORT1_MRCS2                  ((uint32_t volatile *)SPORT1_MRCS2) /* SPORT1 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
#define pSPORT1_MRCS3                  ((uint32_t volatile *)SPORT1_MRCS3) /* SPORT1 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
#define pSPORT1_MTCS0                  ((uint32_t volatile *)SPORT1_MTCS0) /* SPORT1 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
#define pSPORT1_MTCS1                  ((uint32_t volatile *)SPORT1_MTCS1) /* SPORT1 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
#define pSPORT1_MTCS2                  ((uint32_t volatile *)SPORT1_MTCS2) /* SPORT1 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
#define pSPORT1_MTCS3                  ((uint32_t volatile *)SPORT1_MTCS3) /* SPORT1 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
#define pSPORT2_TCR1                   ((uint16_t volatile *)SPORT2_TCR1) /* SPORT2 Transmit Configuration 1 Register */
#define bfin_read_SPORT2_TCR1()        bfin_read16(SPORT2_TCR1)
#define bfin_write_SPORT2_TCR1(val)    bfin_write16(SPORT2_TCR1, val)
#define pSPORT2_TCR2                   ((uint16_t volatile *)SPORT2_TCR2) /* SPORT2 Transmit Configuration 2 Register */
#define bfin_read_SPORT2_TCR2()        bfin_read16(SPORT2_TCR2)
#define bfin_write_SPORT2_TCR2(val)    bfin_write16(SPORT2_TCR2, val)
#define pSPORT2_TCLKDIV                ((uint16_t volatile *)SPORT2_TCLKDIV) /* SPORT2 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT2_TCLKDIV()     bfin_read16(SPORT2_TCLKDIV)
#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
#define pSPORT2_TFSDIV                 ((uint16_t volatile *)SPORT2_TFSDIV) /* SPORT2 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT2_TFSDIV()      bfin_read16(SPORT2_TFSDIV)
#define bfin_write_SPORT2_TFSDIV(val)  bfin_write16(SPORT2_TFSDIV, val)
#define pSPORT2_TX                     ((uint32_t volatile *)SPORT2_TX) /* SPORT2 Transmit Data Register */
#define bfin_write_SPORT2_TX(val)      bfin_write32(SPORT2_TX, val)
#define pSPORT2_RCR1                   ((uint16_t volatile *)SPORT2_RCR1) /* SPORT2 Receive Configuration 1 Register */
#define bfin_read_SPORT2_RCR1()        bfin_read16(SPORT2_RCR1)
#define bfin_write_SPORT2_RCR1(val)    bfin_write16(SPORT2_RCR1, val)
#define pSPORT2_RCR2                   ((uint16_t volatile *)SPORT2_RCR2) /* SPORT2 Receive Configuration 2 Register */
#define bfin_read_SPORT2_RCR2()        bfin_read16(SPORT2_RCR2)
#define bfin_write_SPORT2_RCR2(val)    bfin_write16(SPORT2_RCR2, val)
#define pSPORT2_RCLKDIV                ((uint16_t volatile *)SPORT2_RCLKDIV) /* SPORT2 Receive Serial Clock Divider Register */
#define bfin_read_SPORT2_RCLKDIV()     bfin_read16(SPORT2_RCLKDIV)
#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
#define pSPORT2_RFSDIV                 ((uint16_t volatile *)SPORT2_RFSDIV) /* SPORT2 Receive Frame Sync Divider Register */
#define bfin_read_SPORT2_RFSDIV()      bfin_read16(SPORT2_RFSDIV)
#define bfin_write_SPORT2_RFSDIV(val)  bfin_write16(SPORT2_RFSDIV, val)
#define pSPORT2_RX                     ((uint32_t volatile *)SPORT2_RX) /* SPORT2 Receive Data Register */
#define bfin_read_SPORT2_RX()          bfin_read32(SPORT2_RX)
#define bfin_write_SPORT2_RX(val)      bfin_write32(SPORT2_RX, val)
#define pSPORT2_STAT                   ((uint16_t volatile *)SPORT2_STAT) /* SPORT2 Status Register */
#define bfin_read_SPORT2_STAT()        bfin_read16(SPORT2_STAT)
#define bfin_write_SPORT2_STAT(val)    bfin_write16(SPORT2_STAT, val)
#define pSPORT2_MCMC1                  ((uint16_t volatile *)SPORT2_MCMC1) /* SPORT2 Multi channel Configuration Register 1 */
#define bfin_read_SPORT2_MCMC1()       bfin_read16(SPORT2_MCMC1)
#define bfin_write_SPORT2_MCMC1(val)   bfin_write16(SPORT2_MCMC1, val)
#define pSPORT2_MCMC2                  ((uint16_t volatile *)SPORT2_MCMC2) /* SPORT2 Multi channel Configuration Register 2 */
#define bfin_read_SPORT2_MCMC2()       bfin_read16(SPORT2_MCMC2)
#define bfin_write_SPORT2_MCMC2(val)   bfin_write16(SPORT2_MCMC2, val)
#define pSPORT2_CHNL                   ((uint16_t volatile *)SPORT2_CHNL) /* SPORT2 Current Channel Register */
#define bfin_read_SPORT2_CHNL()        bfin_read16(SPORT2_CHNL)
#define bfin_write_SPORT2_CHNL(val)    bfin_write16(SPORT2_CHNL, val)
#define pSPORT2_MRCS0                  ((uint32_t volatile *)SPORT2_MRCS0) /* SPORT2 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT2_MRCS0()       bfin_read32(SPORT2_MRCS0)
#define bfin_write_SPORT2_MRCS0(val)   bfin_write32(SPORT2_MRCS0, val)
#define pSPORT2_MRCS1                  ((uint32_t volatile *)SPORT2_MRCS1) /* SPORT2 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT2_MRCS1()       bfin_read32(SPORT2_MRCS1)
#define bfin_write_SPORT2_MRCS1(val)   bfin_write32(SPORT2_MRCS1, val)
#define pSPORT2_MRCS2                  ((uint32_t volatile *)SPORT2_MRCS2) /* SPORT2 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT2_MRCS2()       bfin_read32(SPORT2_MRCS2)
#define bfin_write_SPORT2_MRCS2(val)   bfin_write32(SPORT2_MRCS2, val)
#define pSPORT2_MRCS3                  ((uint32_t volatile *)SPORT2_MRCS3) /* SPORT2 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT2_MRCS3()       bfin_read32(SPORT2_MRCS3)
#define bfin_write_SPORT2_MRCS3(val)   bfin_write32(SPORT2_MRCS3, val)
#define pSPORT2_MTCS0                  ((uint32_t volatile *)SPORT2_MTCS0) /* SPORT2 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT2_MTCS0()       bfin_read32(SPORT2_MTCS0)
#define bfin_write_SPORT2_MTCS0(val)   bfin_write32(SPORT2_MTCS0, val)
#define pSPORT2_MTCS1                  ((uint32_t volatile *)SPORT2_MTCS1) /* SPORT2 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT2_MTCS1()       bfin_read32(SPORT2_MTCS1)
#define bfin_write_SPORT2_MTCS1(val)   bfin_write32(SPORT2_MTCS1, val)
#define pSPORT2_MTCS2                  ((uint32_t volatile *)SPORT2_MTCS2) /* SPORT2 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT2_MTCS2()       bfin_read32(SPORT2_MTCS2)
#define bfin_write_SPORT2_MTCS2(val)   bfin_write32(SPORT2_MTCS2, val)
#define pSPORT2_MTCS3                  ((uint32_t volatile *)SPORT2_MTCS3) /* SPORT2 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT2_MTCS3()       bfin_read32(SPORT2_MTCS3)
#define bfin_write_SPORT2_MTCS3(val)   bfin_write32(SPORT2_MTCS3, val)
#define pSPORT3_TCR1                   ((uint16_t volatile *)SPORT3_TCR1) /* SPORT3 Transmit Configuration 1 Register */
#define bfin_read_SPORT3_TCR1()        bfin_read16(SPORT3_TCR1)
#define bfin_write_SPORT3_TCR1(val)    bfin_write16(SPORT3_TCR1, val)
#define pSPORT3_TCR2                   ((uint16_t volatile *)SPORT3_TCR2) /* SPORT3 Transmit Configuration 2 Register */
#define bfin_read_SPORT3_TCR2()        bfin_read16(SPORT3_TCR2)
#define bfin_write_SPORT3_TCR2(val)    bfin_write16(SPORT3_TCR2, val)
#define pSPORT3_TCLKDIV                ((uint16_t volatile *)SPORT3_TCLKDIV) /* SPORT3 Transmit Serial Clock Divider Register */
#define bfin_read_SPORT3_TCLKDIV()     bfin_read16(SPORT3_TCLKDIV)
#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
#define pSPORT3_TFSDIV                 ((uint16_t volatile *)SPORT3_TFSDIV) /* SPORT3 Transmit Frame Sync Divider Register */
#define bfin_read_SPORT3_TFSDIV()      bfin_read16(SPORT3_TFSDIV)
#define bfin_write_SPORT3_TFSDIV(val)  bfin_write16(SPORT3_TFSDIV, val)
#define pSPORT3_TX                     ((uint32_t volatile *)SPORT3_TX) /* SPORT3 Transmit Data Register */
#define bfin_write_SPORT3_TX(val)      bfin_write32(SPORT3_TX, val)
#define pSPORT3_RCR1                   ((uint16_t volatile *)SPORT3_RCR1) /* SPORT3 Receive Configuration 1 Register */
#define bfin_read_SPORT3_RCR1()        bfin_read16(SPORT3_RCR1)
#define bfin_write_SPORT3_RCR1(val)    bfin_write16(SPORT3_RCR1, val)
#define pSPORT3_RCR2                   ((uint16_t volatile *)SPORT3_RCR2) /* SPORT3 Receive Configuration 2 Register */
#define bfin_read_SPORT3_RCR2()        bfin_read16(SPORT3_RCR2)
#define bfin_write_SPORT3_RCR2(val)    bfin_write16(SPORT3_RCR2, val)
#define pSPORT3_RCLKDIV                ((uint16_t volatile *)SPORT3_RCLKDIV) /* SPORT3 Receive Serial Clock Divider Register */
#define bfin_read_SPORT3_RCLKDIV()     bfin_read16(SPORT3_RCLKDIV)
#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
#define pSPORT3_RFSDIV                 ((uint16_t volatile *)SPORT3_RFSDIV) /* SPORT3 Receive Frame Sync Divider Register */
#define bfin_read_SPORT3_RFSDIV()      bfin_read16(SPORT3_RFSDIV)
#define bfin_write_SPORT3_RFSDIV(val)  bfin_write16(SPORT3_RFSDIV, val)
#define pSPORT3_RX                     ((uint32_t volatile *)SPORT3_RX) /* SPORT3 Receive Data Register */
#define bfin_read_SPORT3_RX()          bfin_read32(SPORT3_RX)
#define bfin_write_SPORT3_RX(val)      bfin_write32(SPORT3_RX, val)
#define pSPORT3_STAT                   ((uint16_t volatile *)SPORT3_STAT) /* SPORT3 Status Register */
#define bfin_read_SPORT3_STAT()        bfin_read16(SPORT3_STAT)
#define bfin_write_SPORT3_STAT(val)    bfin_write16(SPORT3_STAT, val)
#define pSPORT3_MCMC1                  ((uint16_t volatile *)SPORT3_MCMC1) /* SPORT3 Multi channel Configuration Register 1 */
#define bfin_read_SPORT3_MCMC1()       bfin_read16(SPORT3_MCMC1)
#define bfin_write_SPORT3_MCMC1(val)   bfin_write16(SPORT3_MCMC1, val)
#define pSPORT3_MCMC2                  ((uint16_t volatile *)SPORT3_MCMC2) /* SPORT3 Multi channel Configuration Register 2 */
#define bfin_read_SPORT3_MCMC2()       bfin_read16(SPORT3_MCMC2)
#define bfin_write_SPORT3_MCMC2(val)   bfin_write16(SPORT3_MCMC2, val)
#define pSPORT3_CHNL                   ((uint16_t volatile *)SPORT3_CHNL) /* SPORT3 Current Channel Register */
#define bfin_read_SPORT3_CHNL()        bfin_read16(SPORT3_CHNL)
#define bfin_write_SPORT3_CHNL(val)    bfin_write16(SPORT3_CHNL, val)
#define pSPORT3_MRCS0                  ((uint32_t volatile *)SPORT3_MRCS0) /* SPORT3 Multi channel Receive Select Register 0 */
#define bfin_read_SPORT3_MRCS0()       bfin_read32(SPORT3_MRCS0)
#define bfin_write_SPORT3_MRCS0(val)   bfin_write32(SPORT3_MRCS0, val)
#define pSPORT3_MRCS1                  ((uint32_t volatile *)SPORT3_MRCS1) /* SPORT3 Multi channel Receive Select Register 1 */
#define bfin_read_SPORT3_MRCS1()       bfin_read32(SPORT3_MRCS1)
#define bfin_write_SPORT3_MRCS1(val)   bfin_write32(SPORT3_MRCS1, val)
#define pSPORT3_MRCS2                  ((uint32_t volatile *)SPORT3_MRCS2) /* SPORT3 Multi channel Receive Select Register 2 */
#define bfin_read_SPORT3_MRCS2()       bfin_read32(SPORT3_MRCS2)
#define bfin_write_SPORT3_MRCS2(val)   bfin_write32(SPORT3_MRCS2, val)
#define pSPORT3_MRCS3                  ((uint32_t volatile *)SPORT3_MRCS3) /* SPORT3 Multi channel Receive Select Register 3 */
#define bfin_read_SPORT3_MRCS3()       bfin_read32(SPORT3_MRCS3)
#define bfin_write_SPORT3_MRCS3(val)   bfin_write32(SPORT3_MRCS3, val)
#define pSPORT3_MTCS0                  ((uint32_t volatile *)SPORT3_MTCS0) /* SPORT3 Multi channel Transmit Select Register 0 */
#define bfin_read_SPORT3_MTCS0()       bfin_read32(SPORT3_MTCS0)
#define bfin_write_SPORT3_MTCS0(val)   bfin_write32(SPORT3_MTCS0, val)
#define pSPORT3_MTCS1                  ((uint32_t volatile *)SPORT3_MTCS1) /* SPORT3 Multi channel Transmit Select Register 1 */
#define bfin_read_SPORT3_MTCS1()       bfin_read32(SPORT3_MTCS1)
#define bfin_write_SPORT3_MTCS1(val)   bfin_write32(SPORT3_MTCS1, val)
#define pSPORT3_MTCS2                  ((uint32_t volatile *)SPORT3_MTCS2) /* SPORT3 Multi channel Transmit Select Register 2 */
#define bfin_read_SPORT3_MTCS2()       bfin_read32(SPORT3_MTCS2)
#define bfin_write_SPORT3_MTCS2(val)   bfin_write32(SPORT3_MTCS2, val)
#define pSPORT3_MTCS3                  ((uint32_t volatile *)SPORT3_MTCS3) /* SPORT3 Multi channel Transmit Select Register 3 */
#define bfin_read_SPORT3_MTCS3()       bfin_read32(SPORT3_MTCS3)
#define bfin_write_SPORT3_MTCS3(val)   bfin_write32(SPORT3_MTCS3, val)
#define pUART0_DLL                     ((uint16_t volatile *)UART0_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
#define pUART0_DLH                     ((uint16_t volatile *)UART0_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
#define pUART0_GCTL                    ((uint16_t volatile *)UART0_GCTL) /* Global Control Register */
#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
#define pUART0_LCR                     ((uint16_t volatile *)UART0_LCR) /* Line Control Register */
#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
#define pUART0_MCR                     ((uint16_t volatile *)UART0_MCR) /* Modem Control Register */
#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
#define pUART0_LSR                     ((uint16_t volatile *)UART0_LSR) /* Line Status Register */
#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
#define pUART0_MSR                     ((uint16_t volatile *)UART0_MSR) /* Modem Status Register */
#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
#define pUART0_SCR                     ((uint16_t volatile *)UART0_SCR) /* Scratch Register */
#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
#define pUART0_IER_SET                 ((uint16_t volatile *)UART0_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART0_IER_SET()      bfin_read16(UART0_IER_SET)
#define bfin_write_UART0_IER_SET(val)  bfin_write16(UART0_IER_SET, val)
#define pUART0_IER_CLEAR               ((uint16_t volatile *)UART0_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART0_IER_CLEAR()    bfin_read16(UART0_IER_CLEAR)
#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
#define pUART0_THR                     ((uint16_t volatile *)UART0_THR) /* Transmit Hold Register */
#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
#define pUART0_RBR                     ((uint16_t volatile *)UART0_RBR) /* Receive Buffer Register */
#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
#define pUART1_DLL                     ((uint16_t volatile *)UART1_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
#define pUART1_DLH                     ((uint16_t volatile *)UART1_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
#define pUART1_GCTL                    ((uint16_t volatile *)UART1_GCTL) /* Global Control Register */
#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
#define pUART1_LCR                     ((uint16_t volatile *)UART1_LCR) /* Line Control Register */
#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
#define pUART1_MCR                     ((uint16_t volatile *)UART1_MCR) /* Modem Control Register */
#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
#define pUART1_LSR                     ((uint16_t volatile *)UART1_LSR) /* Line Status Register */
#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
#define pUART1_MSR                     ((uint16_t volatile *)UART1_MSR) /* Modem Status Register */
#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
#define pUART1_SCR                     ((uint16_t volatile *)UART1_SCR) /* Scratch Register */
#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
#define pUART1_IER_SET                 ((uint16_t volatile *)UART1_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART1_IER_SET()      bfin_read16(UART1_IER_SET)
#define bfin_write_UART1_IER_SET(val)  bfin_write16(UART1_IER_SET, val)
#define pUART1_IER_CLEAR               ((uint16_t volatile *)UART1_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART1_IER_CLEAR()    bfin_read16(UART1_IER_CLEAR)
#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
#define pUART1_THR                     ((uint16_t volatile *)UART1_THR) /* Transmit Hold Register */
#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
#define pUART1_RBR                     ((uint16_t volatile *)UART1_RBR) /* Receive Buffer Register */
#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
#define pUART3_DLL                     ((uint16_t volatile *)UART3_DLL) /* Divisor Latch Low Byte */
#define bfin_read_UART3_DLL()          bfin_read16(UART3_DLL)
#define bfin_write_UART3_DLL(val)      bfin_write16(UART3_DLL, val)
#define pUART3_DLH                     ((uint16_t volatile *)UART3_DLH) /* Divisor Latch High Byte */
#define bfin_read_UART3_DLH()          bfin_read16(UART3_DLH)
#define bfin_write_UART3_DLH(val)      bfin_write16(UART3_DLH, val)
#define pUART3_GCTL                    ((uint16_t volatile *)UART3_GCTL) /* Global Control Register */
#define bfin_read_UART3_GCTL()         bfin_read16(UART3_GCTL)
#define bfin_write_UART3_GCTL(val)     bfin_write16(UART3_GCTL, val)
#define pUART3_LCR                     ((uint16_t volatile *)UART3_LCR) /* Line Control Register */
#define bfin_read_UART3_LCR()          bfin_read16(UART3_LCR)
#define bfin_write_UART3_LCR(val)      bfin_write16(UART3_LCR, val)
#define pUART3_MCR                     ((uint16_t volatile *)UART3_MCR) /* Modem Control Register */
#define bfin_read_UART3_MCR()          bfin_read16(UART3_MCR)
#define bfin_write_UART3_MCR(val)      bfin_write16(UART3_MCR, val)
#define pUART3_LSR                     ((uint16_t volatile *)UART3_LSR) /* Line Status Register */
#define bfin_read_UART3_LSR()          bfin_read16(UART3_LSR)
#define bfin_write_UART3_LSR(val)      bfin_write16(UART3_LSR, val)
#define pUART3_MSR                     ((uint16_t volatile *)UART3_MSR) /* Modem Status Register */
#define bfin_read_UART3_MSR()          bfin_read16(UART3_MSR)
#define bfin_write_UART3_MSR(val)      bfin_write16(UART3_MSR, val)
#define pUART3_SCR                     ((uint16_t volatile *)UART3_SCR) /* Scratch Register */
#define bfin_read_UART3_SCR()          bfin_read16(UART3_SCR)
#define bfin_write_UART3_SCR(val)      bfin_write16(UART3_SCR, val)
#define pUART3_IER_SET                 ((uint16_t volatile *)UART3_IER_SET) /* Interrupt Enable Register Set */
#define bfin_read_UART3_IER_SET()      bfin_read16(UART3_IER_SET)
#define bfin_write_UART3_IER_SET(val)  bfin_write16(UART3_IER_SET, val)
#define pUART3_IER_CLEAR               ((uint16_t volatile *)UART3_IER_CLEAR) /* Interrupt Enable Register Clear */
#define bfin_read_UART3_IER_CLEAR()    bfin_read16(UART3_IER_CLEAR)
#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
#define pUART3_THR                     ((uint16_t volatile *)UART3_THR) /* Transmit Hold Register */
#define bfin_read_UART3_THR()          bfin_read16(UART3_THR)
#define bfin_write_UART3_THR(val)      bfin_write16(UART3_THR, val)
#define pUART3_RBR                     ((uint16_t volatile *)UART3_RBR) /* Receive Buffer Register */
#define bfin_read_UART3_RBR()          bfin_read16(UART3_RBR)
#define bfin_write_UART3_RBR(val)      bfin_write16(UART3_RBR, val)

#endif /* __BFIN_CDEF_ADSP_EDN_BF544_extended__ */