summaryrefslogtreecommitdiff
path: root/board/keymile
diff options
context:
space:
mode:
Diffstat (limited to 'board/keymile')
-rw-r--r--board/keymile/km_arm/fpga_config.c26
-rw-r--r--board/keymile/km_arm/km_arm.c4
2 files changed, 30 insertions, 0 deletions
diff --git a/board/keymile/km_arm/fpga_config.c b/board/keymile/km_arm/fpga_config.c
index cbfc7d2175..51a3cfe647 100644
--- a/board/keymile/km_arm/fpga_config.c
+++ b/board/keymile/km_arm/fpga_config.c
@@ -189,6 +189,31 @@ int wait_for_fpga_config(void)
return 0;
}
+#if defined(KM_PCIE_RESET_MPP7)
+
+#define KM_PEX_RST_GPIO_PIN 7
+int fpga_reset(void)
+{
+ if (!check_boco2()) {
+ /* we do not have BOCO2, this is not really used */
+ return 0;
+ }
+
+ printf("PCIe reset through GPIO7: ");
+ /* apply PCIe reset via GPIO */
+ kw_gpio_set_valid(KM_PEX_RST_GPIO_PIN, 1);
+ kw_gpio_direction_output(KM_PEX_RST_GPIO_PIN, 1);
+ kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 0);
+ udelay(1000*10);
+ kw_gpio_set_value(KM_PEX_RST_GPIO_PIN, 1);
+
+ printf(" done\n");
+
+ return 0;
+}
+
+#else
+
#define PRST1 0x4
#define PCIE_RST 0x10
#define TRAFFIC_RST 0x04
@@ -219,6 +244,7 @@ int fpga_reset(void)
return 0;
}
+#endif
/* the FPGA was configured, we configure the BOCO2 so that the EEPROM
* is available from the Bobcat SPI bus */
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index 5f32e70f10..35402c800b 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -46,7 +46,11 @@ static const u32 kwmpp_config[] = {
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
+#if defined(KM_PCIE_RESET_MPP7)
+ MPP7_GPO,
+#else
MPP7_PEX_RST_OUTn,
+#endif
#if defined(CONFIG_SYS_I2C_SOFT)
MPP8_GPIO, /* SDA */
MPP9_GPIO, /* SCL */