diff options
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 20 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 1 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 |
3 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 810313c5c3..1e73d7dd6a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -96,6 +96,15 @@ struct sunxi_ccm_reg { u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ }; +struct sunxi_sysctl_reg { + u8 reserved1[0x24]; /* 0x00 */ + u32 version; /* 0x24 system version (and boot select) */ + u8 reserved2[0x8]; /* 0x28 */ + u32 gmac_clk_cfg; /* 0x30 GMAC clock control */ + u8 reserved3[0x4]; /* 0x34 */ + u32 disp_mux_cfg; /* 0x38 display MUX control */ +}; + /* pll4_periph0_cfg */ #define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */ @@ -116,6 +125,7 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_ENABLE (1 << 31) /* ahb_gate0 fields */ +#define AHB_GATE_OFFSET_GMAC 17 #define AHB_GATE_OFFSET_MCTL 14 /* On sun9i all sdc-s share their ahb gate, so ignore (x) */ @@ -132,6 +142,7 @@ struct sunxi_ccm_reg { #define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) /* ahb_reset0_cfg fields */ +#define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 /* On sun9i all sdc-s share their ahb reset, so ignore (x) */ @@ -143,6 +154,15 @@ struct sunxi_ccm_reg { #define APB1_RESET_TWI_SHIFT 0 #define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) +/* gmac_clk_cfg (in SYSCTL) fields ... these need to be misnamed as CCM_GMAC_CTRL + so we can reuse the same code as for sun6i in board/sunxi/gmac.c */ +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) #ifndef __ASSEMBLY__ unsigned int clock_get_pll4_periph0(void); diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 8ace4e7cb0..ec37bb9afb 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -47,6 +47,7 @@ #define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) /* AHB1 Module */ +#define SUNXI_SYSCTL_BASE (REGS_AHB1_BASE + 0x000000) #define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) #define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) #define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 98c00d84aa..46ca759255 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -145,6 +145,7 @@ enum sunxi_gpio_number { #define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 +#define SUN9I_GPA_GMAC 2 #define SUN6I_GPA_SDC2 5 #define SUN6I_GPA_SDC3 4 #define SUN8I_H3_GPA_UART0 2 |