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Diffstat (limited to 'arch/arm/dts/sun8i-h3.dtsi')
-rw-r--r--arch/arm/dts/sun8i-h3.dtsi189
1 files changed, 133 insertions, 56 deletions
diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi
index 0faa38a843..c2f63c5050 100644
--- a/arch/arm/dts/sun8i-h3.dtsi
+++ b/arch/arm/dts/sun8i-h3.dtsi
@@ -83,12 +83,6 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <24000000>;
- arm,cpu-registers-not-fw-configured;
- };
-
- memory {
- reg = <0x40000000 0x80000000>;
};
clocks {
@@ -131,15 +125,24 @@
compatible = "allwinner,sun6i-a31-pll6-clk";
reg = <0x01c20028 0x4>;
clocks = <&osc24M>;
- clock-output-names = "pll6", "pll6x2", "pll6d2";
+ clock-output-names = "pll6", "pll6x2";
};
- pll8: clk@01c20044 {
- #clock-cells = <1>;
- compatible = "allwinner,sun6i-a31-pll6-clk";
- reg = <0x01c20044 0x4>;
- clocks = <&osc24M>;
- clock-output-names = "pll8", "pll8x2";
+ pll6d2: pll6d2_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll6 0>;
+ clock-output-names = "pll6d2";
+ };
+
+ /* dummy clock until pll6 can be reused */
+ pll8: pll8_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1>;
+ clock-output-names = "pll8";
};
cpu: cpu_clk@01c20050 {
@@ -170,7 +173,7 @@
#clock-cells = <0>;
compatible = "allwinner,sun8i-h3-ahb2-clk";
reg = <0x01c2005c 0x4>;
- clocks = <&ahb1>, <&pll6 2>;
+ clocks = <&ahb1>, <&pll6d2>;
clock-output-names = "ahb2";
};
@@ -213,34 +216,34 @@
<76>, <77>, <78>,
<96>, <97>, <98>,
<112>, <113>,
- <114>, <115>, <116>,
- <128>, <135>;
- clock-output-names = "ahb1_ce", "ahb1_dma", "ahb1_mmc0",
- "ahb1_mmc1", "ahb1_mmc2", "ahb1_nand",
- "ahb1_sdram", "ahb2_gmac", "ahb1_ts",
- "ahb1_hstimer", "ahb1_spi0",
- "ahb1_spi1", "ahb1_otg",
- "ahb1_otg_ehci0", "ahb1_ehic1",
- "ahb1_ehic2", "ahb1_ehic3",
- "ahb1_otg_ohci0", "ahb2_ohic1",
- "ahb2_ohic2", "ahb2_ohic3", "ahb1_ve",
- "ahb1_lcd0", "ahb1_lcd1", "ahb1_deint",
- "ahb1_csi", "ahb1_tve", "ahb1_hdmi",
- "ahb1_de", "ahb1_gpu", "ahb1_msgbox",
- "ahb1_spinlock", "apb1_codec",
- "apb1_spdif", "apb1_pio", "apb1_ths",
- "apb1_i2s0", "apb1_i2s1", "apb1_i2s2",
- "apb2_i2c0", "apb2_i2c1", "apb2_i2c2",
- "apb2_uart0", "apb2_uart1",
- "apb2_uart2", "apb2_uart3", "apb2_scr",
- "ahb1_ephy", "ahb1_dbg";
+ <114>, <115>,
+ <116>, <128>, <135>;
+ clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
+ "bus_mmc1", "bus_mmc2", "bus_nand",
+ "bus_sdram", "bus_gmac", "bus_ts",
+ "bus_hstimer", "bus_spi0",
+ "bus_spi1", "bus_otg",
+ "bus_otg_ehci0", "bus_ehci1",
+ "bus_ehci2", "bus_ehci3",
+ "bus_otg_ohci0", "bus_ohci1",
+ "bus_ohci2", "bus_ohci3", "bus_ve",
+ "bus_lcd0", "bus_lcd1", "bus_deint",
+ "bus_csi", "bus_tve", "bus_hdmi",
+ "bus_de", "bus_gpu", "bus_msgbox",
+ "bus_spinlock", "bus_codec",
+ "bus_spdif", "bus_pio", "bus_ths",
+ "bus_i2s0", "bus_i2s1", "bus_i2s2",
+ "bus_i2c0", "bus_i2c1", "bus_i2c2",
+ "bus_uart0", "bus_uart1",
+ "bus_uart2", "bus_uart3",
+ "bus_scr", "bus_ephy", "bus_dbg";
};
mmc0_clk: clk@01c20088 {
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20088 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
clock-output-names = "mmc0",
"mmc0_output",
"mmc0_sample";
@@ -250,7 +253,7 @@
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c2008c 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
clock-output-names = "mmc1",
"mmc1_output",
"mmc1_sample";
@@ -260,7 +263,7 @@
#clock-cells = <1>;
compatible = "allwinner,sun4i-a10-mmc-clk";
reg = <0x01c20090 0x4>;
- clocks = <&osc24M>, <&pll6 0>, <&pll8 0>;
+ clocks = <&osc24M>, <&pll6 0>, <&pll8>;
clock-output-names = "mmc2",
"mmc2_output",
"mmc2_sample";
@@ -285,6 +288,33 @@
clocks = <&osc24M>, <&pll6 1>, <&pll5>;
clock-output-names = "mbus";
};
+
+ apb0: apb0_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&osc24M>;
+ clock-output-names = "apb0";
+ };
+
+ apb0_gates: clk@01f01428 {
+ compatible = "allwinner,sun8i-h3-apb0-gates-clk",
+ "allwinner,sun4i-a10-gates-clk";
+ reg = <0x01f01428 0x4>;
+ #clock-cells = <1>;
+ clocks = <&apb0>;
+ clock-indices = <0>, <1>;
+ clock-output-names = "apb0_pio", "apb0_ir";
+ };
+
+ ir_clk: ir_clk@01f01454 {
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01f01454 0x4>;
+ #clock-cells = <0>;
+ clocks = <&osc32k>, <&osc24M>;
+ clock-output-names = "ir";
+ };
};
soc {
@@ -298,7 +328,7 @@
reg = <0x01c02000 0x1000>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 6>;
- resets = <&bus_rst 6>;
+ resets = <&ahb_rst 6>;
#dma-cells = <1>;
};
@@ -313,7 +343,7 @@
"mmc",
"output",
"sample";
- resets = <&bus_rst 8>;
+ resets = <&ahb_rst 8>;
reset-names = "ahb";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -332,7 +362,7 @@
"mmc",
"output",
"sample";
- resets = <&bus_rst 9>;
+ resets = <&ahb_rst 9>;
reset-names = "ahb";
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -351,7 +381,7 @@
"mmc",
"output",
"sample";
- resets = <&bus_rst 10>;
+ resets = <&ahb_rst 10>;
reset-names = "ahb";
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -396,7 +426,7 @@
reg = <0x01c1b000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 25>, <&bus_gates 29>;
- resets = <&bus_rst 25>, <&bus_rst 29>;
+ resets = <&ahb_rst 25>, <&ahb_rst 29>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
@@ -408,7 +438,7 @@
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 29>, <&bus_gates 25>,
<&usb_clk 17>;
- resets = <&bus_rst 29>, <&bus_rst 25>;
+ resets = <&ahb_rst 29>, <&ahb_rst 25>;
phys = <&usbphy 1>;
phy-names = "usb";
status = "disabled";
@@ -419,7 +449,7 @@
reg = <0x01c1c000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 26>, <&bus_gates 30>;
- resets = <&bus_rst 26>, <&bus_rst 30>;
+ resets = <&ahb_rst 26>, <&ahb_rst 30>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
@@ -431,7 +461,7 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 30>, <&bus_gates 26>,
<&usb_clk 18>;
- resets = <&bus_rst 30>, <&bus_rst 26>;
+ resets = <&ahb_rst 30>, <&ahb_rst 26>;
phys = <&usbphy 2>;
phy-names = "usb";
status = "disabled";
@@ -442,7 +472,7 @@
reg = <0x01c1d000 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 27>, <&bus_gates 31>;
- resets = <&bus_rst 27>, <&bus_rst 31>;
+ resets = <&ahb_rst 27>, <&ahb_rst 31>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
@@ -454,7 +484,7 @@
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bus_gates 31>, <&bus_gates 27>,
<&usb_clk 19>;
- resets = <&bus_rst 31>, <&bus_rst 27>;
+ resets = <&ahb_rst 31>, <&ahb_rst 27>;
phys = <&usbphy 3>;
phy-names = "usb";
status = "disabled";
@@ -469,7 +499,7 @@
gpio-controller;
#gpio-cells = <3>;
interrupt-controller;
- #interrupt-cells = <2>;
+ #interrupt-cells = <3>;
uart0_pins_a: uart0@0 {
allwinner,pins = "PA4", "PA5";
@@ -502,10 +532,22 @@
};
};
- bus_rst: reset@01c202c0 {
+ ahb_rst: reset@01c202c0 {
#reset-cells = <1>;
- compatible = "allwinner,sun8i-h3-bus-reset";
- reg = <0x01c202c0 0x1c>;
+ compatible = "allwinner,sun6i-a31-ahb1-reset";
+ reg = <0x01c202c0 0xc>;
+ };
+
+ apb1_rst: reset@01c202d0 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d0 0x4>;
+ };
+
+ apb2_rst: reset@01c202d8 {
+ #reset-cells = <1>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ reg = <0x01c202d8 0x4>;
};
timer@01c20c00 {
@@ -529,7 +571,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 112>;
- resets = <&bus_rst 144>;
+ resets = <&apb2_rst 16>;
dmas = <&dma 6>, <&dma 6>;
dma-names = "rx", "tx";
status = "disabled";
@@ -542,7 +584,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 113>;
- resets = <&bus_rst 145>;
+ resets = <&apb2_rst 17>;
dmas = <&dma 7>, <&dma 7>;
dma-names = "rx", "tx";
status = "disabled";
@@ -555,7 +597,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 114>;
- resets = <&bus_rst 146>;
+ resets = <&apb2_rst 18>;
dmas = <&dma 8>, <&dma 8>;
dma-names = "rx", "tx";
status = "disabled";
@@ -568,7 +610,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&bus_gates 115>;
- resets = <&bus_rst 147>;
+ resets = <&apb2_rst 19>;
dmas = <&dma 9>, <&dma 9>;
dma-names = "rx", "tx";
status = "disabled";
@@ -591,5 +633,40 @@
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ apb0_reset: reset@01f014b0 {
+ reg = <0x01f014b0 0x4>;
+ compatible = "allwinner,sun6i-a31-clock-reset";
+ #reset-cells = <1>;
+ };
+
+ ir: ir@01f02000 {
+ compatible = "allwinner,sun5i-a13-ir";
+ clocks = <&apb0_gates 1>, <&ir_clk>;
+ clock-names = "apb", "ir";
+ resets = <&apb0_reset 1>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x01f02000 0x40>;
+ status = "disabled";
+ };
+
+ r_pio: pinctrl@01f02c00 {
+ compatible = "allwinner,sun8i-h3-r-pinctrl";
+ reg = <0x01f02c00 0x400>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb0_gates 0>;
+ resets = <&apb0_reset 0>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ ir_pins_a: ir@0 {
+ allwinner,pins = "PL11";
+ allwinner,function = "s_cir_rx";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+ };
};
};
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 11:08:55 +0000