Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

Conflicts:
	drivers/mtd/nand/mxc_nand_spl.c
	include/configs/m28evk.h

12 files changed, 722 insertions, 83 deletions

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 0c1cd831e0..510cb28ad5 100644
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -31,7 +31,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
+#include <asm/imx-common/regs-apbh.h>
 
 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
 
@@ -226,7 +227,7 @@ static int mxs_dma_reset(int channel)
 #if defined(CONFIG_MX23)
 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
 	uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif defined(CONFIG_MX28)
+#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
 	uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 8cdc3b649c..5d869b47ad 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -28,8 +28,10 @@ LIB	:= $(obj)libmisc.o
 COBJS-$(CONFIG_ALI152X) += ali512x.o
 COBJS-$(CONFIG_DS4510)  += ds4510.o
 COBJS-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
+COBJS-$(CONFIG_FSL_IIM) += fsl_iim.o
 COBJS-$(CONFIG_GPIO_LED) += gpio_led.o
 COBJS-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
+COBJS-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 COBJS-$(CONFIG_NS87308) += ns87308.o
 COBJS-$(CONFIG_PDSP188x) += pdsp188x.o
 COBJS-$(CONFIG_STATUS_LED) += status_led.o
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
new file mode 100644
index 0000000000..9179fbb0db
--- /dev/null
+++ b/drivers/misc/fsl_iim.c
@@ -0,0 +1,286 @@
+/*
+ * (C) Copyright 2009-2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on the mpc512x iim code:
+ * Copyright 2008 Silicon Turnkey Express, Inc.
+ * Martha Marx <mmarx@silicontkx.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#ifndef CONFIG_MPC512X
+#include <asm/arch/imx-regs.h>
+#endif
+
+/* FSL IIM-specific constants */
+#define STAT_BUSY		0x80
+#define STAT_PRGD		0x02
+#define STAT_SNSD		0x01
+
+#define STATM_PRGD_M		0x02
+#define STATM_SNSD_M		0x01
+
+#define ERR_PRGE		0x80
+#define ERR_WPE			0x40
+#define ERR_OPE			0x20
+#define ERR_RPE			0x10
+#define ERR_WLRE		0x08
+#define ERR_SNSE		0x04
+#define ERR_PARITYE		0x02
+
+#define EMASK_PRGE_M		0x80
+#define EMASK_WPE_M		0x40
+#define EMASK_OPE_M		0x20
+#define EMASK_RPE_M		0x10
+#define EMASK_WLRE_M		0x08
+#define EMASK_SNSE_M		0x04
+#define EMASK_PARITYE_M		0x02
+
+#define FCTL_DPC		0x80
+#define FCTL_PRG_LENGTH_MASK	0x70
+#define FCTL_ESNS_N		0x08
+#define FCTL_ESNS_0		0x04
+#define FCTL_ESNS_1		0x02
+#define FCTL_PRG		0x01
+
+#define UA_A_BANK_MASK		0x38
+#define UA_A_ROWH_MASK		0x07
+
+#define LA_A_ROWL_MASK		0xf8
+#define LA_A_BIT_MASK		0x07
+
+#define PREV_PROD_REV_MASK	0xf8
+#define PREV_PROD_VT_MASK	0x07
+
+/* Select the correct accessors depending on endianness */
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#define iim_read32		in_le32
+#define iim_write32		out_le32
+#define iim_clrsetbits32	clrsetbits_le32
+#define iim_clrbits32		clrbits_le32
+#define iim_setbits32		setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define iim_read32		in_be32
+#define iim_write32		out_be32
+#define iim_clrsetbits32	clrsetbits_be32
+#define iim_clrbits32		clrbits_be32
+#define iim_setbits32		setbits_be32
+#else
+#error Endianess is not defined: please fix to continue
+#endif
+
+/* IIM control registers */
+struct fsl_iim {
+	u32 stat;
+	u32 statm;
+	u32 err;
+	u32 emask;
+	u32 fctl;
+	u32 ua;
+	u32 la;
+	u32 sdat;
+	u32 prev;
+	u32 srev;
+	u32 prg_p;
+	u32 scs[0x1f5];
+	struct {
+		u32 word[0x100];
+	} bank[8];
+};
+
+static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
+				const char *caller)
+{
+	*regs = (struct fsl_iim *)IIM_BASE_ADDR;
+
+	if (bank >= ARRAY_SIZE((*regs)->bank) ||
+			word >= ARRAY_SIZE((*regs)->bank[0].word) ||
+			!assert) {
+		printf("fsl_iim %s(): Invalid argument\n", caller);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void clear_status(struct fsl_iim *regs)
+{
+	iim_setbits32(&regs->stat, 0);
+	iim_setbits32(&regs->err, 0);
+}
+
+static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
+{
+	*stat = iim_read32(&regs->stat);
+	*err = iim_read32(&regs->err);
+	clear_status(regs);
+}
+
+static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
+			const char *caller)
+{
+	int ret;
+
+	ret = prepare_access(regs, bank, word, val != NULL, caller);
+	if (ret)
+		return ret;
+
+	clear_status(*regs);
+
+	return 0;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	struct fsl_iim *regs;
+	u32 stat, err;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	*val = iim_read32(&regs->bank[bank].word[word]);
+	finish_access(regs, &stat, &err);
+
+	if (err & ERR_RPE) {
+		puts("fsl_iim fuse_read(): Read protect error\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
+				u32 fctl, u32 *stat, u32 *err)
+{
+	iim_write32(&regs->ua, bank << 3 | word >> 5);
+	iim_write32(&regs->la, (word << 3 | bit) & 0xff);
+	if (fctl == FCTL_PRG)
+		iim_write32(&regs->prg_p, 0xaa);
+	iim_setbits32(&regs->fctl, fctl);
+	while (iim_read32(&regs->stat) & STAT_BUSY)
+		udelay(20);
+	finish_access(regs, stat, err);
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	struct fsl_iim *regs;
+	u32 stat, err;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
+
+	if (err & ERR_SNSE) {
+		puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
+		return -EIO;
+	}
+
+	if (!(stat & STAT_SNSD)) {
+		puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
+		return -EIO;
+	}
+
+	*val = iim_read32(&regs->sdat);
+	return 0;
+}
+
+static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
+{
+	u32 stat, err;
+
+	clear_status(regs);
+	direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
+	iim_write32(&regs->prg_p, 0x00);
+
+	if (err & ERR_PRGE) {
+		puts("fsl_iim fuse_prog(): Program error\n");
+		return -EIO;
+	}
+
+	if (err & ERR_WPE) {
+		puts("fsl_iim fuse_prog(): Write protect error\n");
+		return -EIO;
+	}
+
+	if (!(stat & STAT_PRGD)) {
+		puts("fsl_iim fuse_prog(): Program did not complete\n");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
+				const char *caller)
+{
+	return prepare_access(regs, bank, word, !(val & ~0xff), caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	struct fsl_iim *regs;
+	u32 bit;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	for (bit = 0; val; bit++, val >>= 1)
+		if (val & 0x01) {
+			ret = prog_bit(regs, bank, word, bit);
+			if (ret)
+				return ret;
+		}
+
+	return 0;
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	struct fsl_iim *regs;
+	u32 stat, err;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	clear_status(regs);
+	iim_write32(&regs->bank[bank].word[word], val);
+	finish_access(regs, &stat, &err);
+
+	if (err & ERR_OPE) {
+		puts("fsl_iim fuse_override(): Override protect error\n");
+		return -EIO;
+	}
+
+	return 0;
+}
diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
new file mode 100644
index 0000000000..0095b471bd
--- /dev/null
+++ b/drivers/misc/mxc_ocotp.c
@@ -0,0 +1,216 @@
+/*
+ * (C) Copyright 2013 ADVANSEE
+ * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
+ *
+ * Based on Dirk Behme's
+ * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c,
+ * which is based on Freescale's
+ * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6,
+ * which is:
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <fuse.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+
+#define BO_CTRL_WR_UNLOCK		16
+#define BM_CTRL_WR_UNLOCK		0xffff0000
+#define BV_CTRL_WR_UNLOCK_KEY		0x3e77
+#define BM_CTRL_ERROR			0x00000200
+#define BM_CTRL_BUSY			0x00000100
+#define BO_CTRL_ADDR			0
+#define BM_CTRL_ADDR			0x0000007f
+
+#define BO_TIMING_STROBE_READ		16
+#define BM_TIMING_STROBE_READ		0x003f0000
+#define BV_TIMING_STROBE_READ_NS	37
+#define BO_TIMING_RELAX			12
+#define BM_TIMING_RELAX			0x0000f000
+#define BV_TIMING_RELAX_NS		17
+#define BO_TIMING_STROBE_PROG		0
+#define BM_TIMING_STROBE_PROG		0x00000fff
+#define BV_TIMING_STROBE_PROG_US	10
+
+#define BM_READ_CTRL_READ_FUSE		0x00000001
+
+#define BF(value, field)		(((value) << BO_##field) & BM_##field)
+
+#define WRITE_POSTAMBLE_US		2
+
+static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us)
+{
+	while (readl(&regs->ctrl) & BM_CTRL_BUSY)
+		udelay(delay_us);
+}
+
+static void clear_error(struct ocotp_regs *regs)
+{
+	writel(BM_CTRL_ERROR, &regs->ctrl_clr);
+}
+
+static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word,
+				int assert, const char *caller)
+{
+	*regs = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+
+	if (bank >= ARRAY_SIZE((*regs)->bank) ||
+			word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 ||
+			!assert) {
+		printf("mxc_ocotp %s(): Invalid argument\n", caller);
+		return -EINVAL;
+	}
+
+	enable_ocotp_clk(1);
+
+	wait_busy(*regs, 1);
+	clear_error(*regs);
+
+	return 0;
+}
+
+static int finish_access(struct ocotp_regs *regs, const char *caller)
+{
+	u32 err;
+
+	err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
+	clear_error(regs);
+
+	enable_ocotp_clk(0);
+
+	if (err) {
+		printf("mxc_ocotp %s(): Access protect error\n", caller);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val,
+			const char *caller)
+{
+	return prepare_access(regs, bank, word, val != NULL, caller);
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	*val = readl(&regs->bank[bank].fuse_regs[word << 2]);
+
+	return finish_access(regs, __func__);
+}
+
+static void set_timing(struct ocotp_regs *regs)
+{
+	u32 ipg_clk;
+	u32 relax, strobe_read, strobe_prog;
+	u32 timing;
+
+	ipg_clk = mxc_get_clock(MXC_IPG_CLK);
+
+	relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1;
+	strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS,
+					1000000000) + 2 * (relax + 1) - 1;
+	strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) +
+			2 * (relax + 1) - 1;
+
+	timing = BF(strobe_read, TIMING_STROBE_READ) |
+			BF(relax, TIMING_RELAX) |
+			BF(strobe_prog, TIMING_STROBE_PROG);
+
+	clrsetbits_le32(&regs->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX |
+			BM_TIMING_STROBE_PROG, timing);
+}
+
+static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word,
+				int write)
+{
+	u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0;
+	u32 addr = bank << 3 | word;
+
+	set_timing(regs);
+	clrsetbits_le32(&regs->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR,
+			BF(wr_unlock, CTRL_WR_UNLOCK) |
+			BF(addr, CTRL_ADDR));
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_read(&regs, bank, word, val, __func__);
+	if (ret)
+		return ret;
+
+	setup_direct_access(regs, bank, word, false);
+	writel(BM_READ_CTRL_READ_FUSE, &regs->read_ctrl);
+	wait_busy(regs, 1);
+	*val = readl(&regs->read_fuse_data);
+
+	return finish_access(regs, __func__);
+}
+
+static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
+				const char *caller)
+{
+	return prepare_access(regs, bank, word, true, caller);
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, __func__);
+	if (ret)
+		return ret;
+
+	setup_direct_access(regs, bank, word, true);
+	writel(val, &regs->data);
+	wait_busy(regs, BV_TIMING_STROBE_PROG_US);
+	udelay(WRITE_POSTAMBLE_US);
+
+	return finish_access(regs, __func__);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	struct ocotp_regs *regs;
+	int ret;
+
+	ret = prepare_write(&regs, bank, word, __func__);
+	if (ret)
+		return ret;
+
+	writel(val, &regs->bank[bank].fuse_regs[word << 2]);
+
+	return finish_access(regs, __func__);
+}
diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index a89660f130..fdaf9c763e 100644
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -41,7 +41,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 #include <bouncebuf.h>
 
 struct mxsmmc_priv {
diff --git a/drivers/mtd/nand/mxc_nand_spl.c b/drivers/mtd/nand/mxc_nand_spl.c
index edc589e5b7..f13d5fc581 100644
--- a/drivers/mtd/nand/mxc_nand_spl.c
+++ b/drivers/mtd/nand/mxc_nand_spl.c
@@ -290,7 +290,7 @@ static int is_badblock(int pagenumber)
 	return 0;
 }
 
-static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
+int nand_spl_load_image(uint32_t from, unsigned int size, void *buf)
 {
 	int i;
 	unsigned int page;
@@ -303,6 +303,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
 	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
 	i = 0;
 
+	size = roundup(size, CONFIG_SYS_NAND_PAGE_SIZE);
 	while (i < size / CONFIG_SYS_NAND_PAGE_SIZE) {
 		if (nfc_read_page(page, buf) < 0)
 			return -1;
@@ -332,6 +333,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
 	return 0;
 }
 
+#ifndef CONFIG_SPL_FRAMEWORK
 /*
  * The main entry for NAND booting. It's necessary that SDRAM is already
  * configured and available since this code loads the main U-Boot image
@@ -345,8 +347,9 @@ void nand_boot(void)
 	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
 	 * be aligned to full pages
 	 */
-	if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
-		       (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
+	if (!nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+			CONFIG_SYS_NAND_U_BOOT_SIZE,
+			(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
 		/* Copy from NAND successful, start U-boot */
 		uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
 		uboot();
@@ -355,3 +358,4 @@ void nand_boot(void)
 		hang();
 	}
 }
+#endif
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index e38e151254..398e4ddc15 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -34,12 +34,19 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/imx-common/regs-bch.h>
+#include <asm/imx-common/regs-gpmi.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 
 #define	MXS_NAND_DMA_DESCRIPTOR_COUNT		4
 
 #define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE		512
+#if defined(CONFIG_MX6)
+#define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT	2
+#else
+#define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT	0
+#endif
 #define	MXS_NAND_METADATA_SIZE			10
 
 #define	MXS_NAND_COMMAND_BUFFER_SIZE		32
@@ -980,14 +987,16 @@ static int mxs_nand_scan_bbt(struct mtd_info *mtd)
 	tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
 	tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
 		<< BCH_FLASHLAYOUT0_ECC0_OFFSET;
-	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+		>> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
 	writel(tmp, &bch_regs->hw_bch_flash0layout0);
 
 	tmp = (mtd->writesize + mtd->oobsize)
 		<< BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
 	tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
 		<< BCH_FLASHLAYOUT1_ECCN_OFFSET;
-	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+	tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
+		>> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
 	writel(tmp, &bch_regs->hw_bch_flash0layout1);
 
 	/* Set *all* chip selects to use layout 0 */
diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index aa999f9a94..db98a136e6 100644
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -31,7 +31,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
-#include <asm/arch/dma.h>
+#include <asm/imx-common/dma.h>
 
 #define	MXS_SPI_MAX_TIMEOUT	1000000
 #define	MXS_SPI_PORT_OFFSET	0x2000
diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index adbed5c90c..f43c38da61 100644
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -21,8 +21,6 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/mx5x_pins.h>
-#include <asm/arch/iomux.h>
 
 #include "ehci.h"
 
@@ -87,77 +85,6 @@
 /* USB_CTRL_1 */
 #define MXC_USB_CTRL_UH1_EXT_CLK_EN	(1 << 25)
 
-/* USB pin configuration */
-#define USB_PAD_CONFIG	(PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \
-			PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \
-			PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL)
-
-#ifdef CONFIG_MX51
-/*
- * Configure the MX51 USB H1 IOMUX
- */
-void setup_iomux_usb_h1(void)
-{
-	mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_STP, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_CLK, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_CLK, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DIR, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DIR, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_NXT, USB_PAD_CONFIG);
-
-	mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA1, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA1, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA2, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA2, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA4, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA4, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA5, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA5, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA6, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA6, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_USBH1_DATA7, IOMUX_CONFIG_ALT0);
-	mxc_iomux_set_pad(MX51_PIN_USBH1_DATA7, USB_PAD_CONFIG);
-}
-
-/*
- * Configure the MX51 USB H2 IOMUX
- */
-void setup_iomux_usb_h2(void)
-{
-	mxc_request_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A24, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A25, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A26, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_A27, USB_PAD_CONFIG);
-
-	mxc_request_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D16, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D17, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D18, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D19, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D20, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D21, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D22, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D22, USB_PAD_CONFIG);
-	mxc_request_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
-	mxc_iomux_set_pad(MX51_PIN_EIM_D23, USB_PAD_CONFIG);
-}
-#endif
-
 int mxc_set_usbcontrol(int port, unsigned int flags)
 {
 	unsigned int v;
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 53952ab07e..68ff34bfd5 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+COBJS-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 61e1058adc..0793f07f24 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -151,6 +151,10 @@
 #endif
 #endif
 
+#ifdef CONFIG_VIDEO_MXS
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
 /*
  * Defines for the MB862xx driver
  */
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
new file mode 100644
index 0000000000..461ff6e860
--- /dev/null
+++ b/drivers/video/mxsfb.c
@@ -0,0 +1,189 @@
+/*
+ * Freescale i.MX23/i.MX28 LCDIF driver
+ *
+ * Copyright (C) 2011-2013 Marek Vasut <marex@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <malloc.h>
+#include <video_fb.h>
+
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+
+#include "videomodes.h"
+
+#define	PS2KHZ(ps)	(1000000000UL / (ps))
+
+static GraphicDevice panel;
+
+/*
+ * DENX M28EVK:
+ * setenv videomode
+ * video=ctfb:x:800,y:480,depth:18,mode:0,pclk:30066,
+ *       le:0,ri:256,up:0,lo:45,hs:1,vs:1,sync:100663296,vmode:0
+ */
+
+static void mxs_lcd_init(GraphicDevice *panel,
+			struct ctfb_res_modes *mode, int bpp)
+{
+	struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
+	uint32_t word_len = 0, bus_width = 0;
+	uint8_t valid_data = 0;
+
+	/* Kick in the LCDIF clock */
+	mxs_set_lcdclk(PS2KHZ(mode->pixclock));
+
+	/* Restart the LCDIF block */
+	mxs_reset_block(&regs->hw_lcdif_ctrl_reg);
+
+	switch (bpp) {
+	case 24:
+		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT;
+		valid_data = 0x7;
+		break;
+	case 18:
+		word_len = LCDIF_CTRL_WORD_LENGTH_24BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT;
+		valid_data = 0x7;
+		break;
+	case 16:
+		word_len = LCDIF_CTRL_WORD_LENGTH_16BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT;
+		valid_data = 0xf;
+		break;
+	case 8:
+		word_len = LCDIF_CTRL_WORD_LENGTH_8BIT;
+		bus_width = LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT;
+		valid_data = 0xf;
+		break;
+	}
+
+	writel(bus_width | word_len | LCDIF_CTRL_DOTCLK_MODE |
+		LCDIF_CTRL_BYPASS_COUNT | LCDIF_CTRL_LCDIF_MASTER,
+		&regs->hw_lcdif_ctrl);
+
+	writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
+		&regs->hw_lcdif_ctrl1);
+	writel((mode->yres << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | mode->xres,
+		&regs->hw_lcdif_transfer_count);
+
+	writel(LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL |
+		LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+		LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT |
+		mode->vsync_len, &regs->hw_lcdif_vdctrl0);
+	writel(mode->upper_margin + mode->lower_margin +
+		mode->vsync_len + mode->yres,
+		&regs->hw_lcdif_vdctrl1);
+	writel((mode->hsync_len << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) |
+		(mode->left_margin + mode->right_margin +
+		mode->hsync_len + mode->xres),
+		&regs->hw_lcdif_vdctrl2);
+	writel(((mode->left_margin + mode->hsync_len) <<
+		LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) |
+		(mode->upper_margin + mode->vsync_len),
+		&regs->hw_lcdif_vdctrl3);
+	writel((0 << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) | mode->xres,
+		&regs->hw_lcdif_vdctrl4);
+
+	writel(panel->frameAdrs, &regs->hw_lcdif_cur_buf);
+	writel(panel->frameAdrs, &regs->hw_lcdif_next_buf);
+
+	/* Flush FIFO first */
+	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_set);
+
+	/* Sync signals ON */
+	setbits_le32(&regs->hw_lcdif_vdctrl4, LCDIF_VDCTRL4_SYNC_SIGNALS_ON);
+
+	/* FIFO cleared */
+	writel(LCDIF_CTRL1_FIFO_CLEAR, &regs->hw_lcdif_ctrl1_clr);
+
+	/* RUN! */
+	writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
+}
+
+void *video_hw_init(void)
+{
+	int bpp = -1;
+	char *penv;
+	void *fb;
+	struct ctfb_res_modes mode;
+
+	puts("Video: ");
+
+	/* Suck display configuration from "videomode" variable */
+	penv = getenv("videomode");
+	if (!penv) {
+		printf("MXSFB: 'videomode' variable not set!");
+		return NULL;
+	}
+
+	bpp = video_get_params(&mode, penv);
+
+	/* fill in Graphic device struct */
+	sprintf(panel.modeIdent, "%dx%dx%d",
+			mode.xres, mode.yres, bpp);
+
+	panel.winSizeX = mode.xres;
+	panel.winSizeY = mode.yres;
+	panel.plnSizeX = mode.xres;
+	panel.plnSizeY = mode.yres;
+
+	switch (bpp) {
+	case 24:
+	case 18:
+		panel.gdfBytesPP = 4;
+		panel.gdfIndex = GDF_32BIT_X888RGB;
+		break;
+	case 16:
+		panel.gdfBytesPP = 2;
+		panel.gdfIndex = GDF_16BIT_565RGB;
+		break;
+	case 8:
+		panel.gdfBytesPP = 1;
+		panel.gdfIndex = GDF__8BIT_INDEX;
+		break;
+	default:
+		printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
+		return NULL;
+	}
+
+	panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
+
+	/* Allocate framebuffer */
+	fb = malloc(panel.memSize);
+	if (!fb) {
+		printf("MXSFB: Error allocating framebuffer!\n");
+		return NULL;
+	}
+
+	/* Wipe framebuffer */
+	memset(fb, 0, panel.memSize);
+
+	panel.frameAdrs = (u32)fb;
+
+	printf("%s\n", panel.modeIdent);
+
+	/* Start framebuffer */
+	mxs_lcd_init(&panel, &mode, bpp);
+
+	return (void *)&panel;
+}