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authorJagan Teki <jteki@openedev.com>2015-10-23 01:36:06 +0530
committerJagan Teki <jteki@openedev.com>2015-10-27 23:19:29 +0530
commitb7e83b087c0464b2e52240c2ebb1356125cca93e (patch)
treebe4da29828f5a0e8ba1f439b568552fdc93850ef /drivers
parentc0d1ea4acd53304f9f749790424586f52547a99a (diff)
spi: cadence_qspi_apb: Use BIT macro
Replace numerical bit shift with BIT macro in cadence_qspi_apb :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Acked-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/spi/cadence_qspi_apb.c28
1 files changed, 14 insertions, 14 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index d05340716e..7786dd65f5 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -58,10 +58,10 @@
#define CQSPI_REG_CONFIG 0x00
#define CQSPI_REG_CONFIG_CLK_POL_LSB 1
#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
-#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0)
-#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7)
-#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9)
-#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18)
+#define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
+#define CQSPI_REG_CONFIG_DIRECT_MASK BIT(7)
+#define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
+#define CQSPI_REG_CONFIG_XIP_IMM_MASK BIT(18)
#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
#define CQSPI_REG_CONFIG_BAUD_LSB 19
#define CQSPI_REG_CONFIG_IDLE_LSB 31
@@ -122,18 +122,18 @@
#define CQSPI_REG_IRQMASK 0x44
#define CQSPI_REG_INDIRECTRD 0x60
-#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
-#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1)
-#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2)
-#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5)
+#define CQSPI_REG_INDIRECTRD_START_MASK BIT(0)
+#define CQSPI_REG_INDIRECTRD_CANCEL_MASK BIT(1)
+#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK BIT(2)
+#define CQSPI_REG_INDIRECTRD_DONE_MASK BIT(5)
#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
#define CQSPI_REG_INDIRECTRDBYTES 0x6C
#define CQSPI_REG_CMDCTRL 0x90
-#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0)
-#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1)
+#define CQSPI_REG_CMDCTRL_EXECUTE_MASK BIT(0)
+#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK BIT(1)
#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
@@ -149,10 +149,10 @@
#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
#define CQSPI_REG_INDIRECTWR 0x70
-#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
-#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1)
-#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2)
-#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5)
+#define CQSPI_REG_INDIRECTWR_START_MASK BIT(0)
+#define CQSPI_REG_INDIRECTWR_CANCEL_MASK BIT(1)
+#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK BIT(2)
+#define CQSPI_REG_INDIRECTWR_DONE_MASK BIT(5)
#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78