Merge remote-tracking branch 'u-boot/master'

Conflicts:
	boards.cfg

Conflicts were trivial once u-boot-arm/master boards.cfg was
reformatted (commit 6130c146) to match u-boot/master's own
reformatting (commit 1b37fa83).

24 files changed, 344 insertions, 369 deletions

diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c
index 6eab1b51e5..7054056140 100644
--- a/drivers/fpga/spartan2.c
+++ b/drivers/fpga/spartan2.c
@@ -31,29 +31,29 @@
 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_sp_info(Xilinx_desc *desc ); */
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_sp_info(xilinx_desc *desc ); */
 
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan2_ss_info(Xilinx_desc *desc ); */
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan2_ss_info(xilinx_desc *desc ); */
 
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Generic Implementation */
-int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
-		ret_val = Spartan2_ss_load (desc, buf, bsize);
+		ret_val = spartan2_ss_load(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
-		ret_val = Spartan2_sp_load (desc, buf, bsize);
+		ret_val = spartan2_sp_load(desc, buf, bsize);
 		break;
 
 	default:
@@ -64,19 +64,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
-		ret_val = Spartan2_ss_dump (desc, buf, bsize);
+		ret_val = spartan2_ss_dump(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
-		ret_val = Spartan2_sp_dump (desc, buf, bsize);
+		ret_val = spartan2_sp_dump(desc, buf, bsize);
 		break;
 
 	default:
@@ -87,7 +87,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Spartan2_info( Xilinx_desc *desc )
+static int spartan2_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -96,10 +96,10 @@ int Spartan2_info( Xilinx_desc *desc )
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Slave Parallel Generic Implementation */
 
-static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
-	Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
+	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
 
 	PRINTF ("%s: start with interface functions @ 0x%p\n",
 			__FUNCTION__, fn);
@@ -248,10 +248,10 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
-	Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns;
+	xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns;
 
 	if (fn) {
 		unsigned char *data = (unsigned char *) buf;
@@ -296,10 +296,10 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 /* ------------------------------------------------------------------------- */
 
-static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
-	Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns;
+	xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns;
 	int i;
 	unsigned char val;
 
@@ -439,7 +439,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	/* Readback is only available through the Slave Parallel and         */
 	/* boundary-scan interfaces.                                         */
@@ -447,3 +447,9 @@ static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 			__FUNCTION__);
 	return FPGA_FAIL;
 }
+
+struct xilinx_fpga_op spartan2_op = {
+	.load = spartan2_load,
+	.dump = spartan2_dump,
+	.info = spartan2_info,
+};
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c
index 3edc5c2c66..5c9412c2f6 100644
--- a/drivers/fpga/spartan3.c
+++ b/drivers/fpga/spartan3.c
@@ -35,29 +35,29 @@
 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100	/* 10 ms */
 #endif
 
-static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan3_sp_info(Xilinx_desc *desc ); */
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_sp_info(xilinx_desc *desc ); */
 
-static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-/* static int Spartan3_ss_info(Xilinx_desc *desc); */
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
+/* static int spartan3_ss_info(xilinx_desc *desc); */
 
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Generic Implementation */
-int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
-		ret_val = Spartan3_ss_load (desc, buf, bsize);
+		ret_val = spartan3_ss_load(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
-		ret_val = Spartan3_sp_load (desc, buf, bsize);
+		ret_val = spartan3_sp_load(desc, buf, bsize);
 		break;
 
 	default:
@@ -68,19 +68,19 @@ int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
-		ret_val = Spartan3_ss_dump (desc, buf, bsize);
+		ret_val = spartan3_ss_dump(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
-		ret_val = Spartan3_sp_dump (desc, buf, bsize);
+		ret_val = spartan3_sp_dump(desc, buf, bsize);
 		break;
 
 	default:
@@ -91,7 +91,7 @@ int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Spartan3_info( Xilinx_desc *desc )
+static int spartan3_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -100,10 +100,10 @@ int Spartan3_info( Xilinx_desc *desc )
 /* ------------------------------------------------------------------------- */
 /* Spartan-II Slave Parallel Generic Implementation */
 
-static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
-	Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+	xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
 
 	PRINTF ("%s: start with interface functions @ 0x%p\n",
 			__FUNCTION__, fn);
@@ -254,10 +254,10 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
-	Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
+	xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns;
 
 	if (fn) {
 		unsigned char *data = (unsigned char *) buf;
@@ -302,10 +302,10 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 /* ------------------------------------------------------------------------- */
 
-static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;	/* assume the worst */
-	Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
+	xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns;
 	int i;
 	unsigned char val;
 
@@ -457,7 +457,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	/* Readback is only available through the Slave Parallel and         */
 	/* boundary-scan interfaces.                                         */
@@ -465,3 +465,9 @@ static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 			__FUNCTION__);
 	return FPGA_FAIL;
 }
+
+struct xilinx_fpga_op spartan3_op = {
+	.load = spartan3_load,
+	.dump = spartan3_dump,
+	.info = spartan3_info,
+};
diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index b5a895d41a..e092147edd 100644
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -84,25 +84,25 @@
 #define CONFIG_SYS_FPGA_WAIT_CONFIG	CONFIG_SYS_HZ/5	/* 200 ms */
 #endif
 
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
-		ret_val = Virtex2_ss_load (desc, buf, bsize);
+		ret_val = virtex2_ss_load(desc, buf, bsize);
 		break;
 
 	case slave_selectmap:
 		PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_load (desc, buf, bsize);
+		ret_val = virtex2_ssm_load(desc, buf, bsize);
 		break;
 
 	default:
@@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
 
 	switch (desc->iface) {
 	case slave_serial:
 		PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ss_dump (desc, buf, bsize);
+		ret_val = virtex2_ss_dump(desc, buf, bsize);
 		break;
 
 	case slave_parallel:
 		PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
-		ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+		ret_val = virtex2_ssm_dump(desc, buf, bsize);
 		break;
 
 	default:
@@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-int Virtex2_info (Xilinx_desc * desc)
+static int virtex2_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc)
  *    INIT_B and DONE lines.  If both are high, configuration has
  *    succeeded. Congratulations!
  */
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
 			__FUNCTION__, __LINE__, fn);
@@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 /*
  * Read the FPGA configuration data
  */
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	int ret_val = FPGA_FAIL;
-	Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+	xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
 	if (fn) {
 		unsigned char *data = (unsigned char *) buf;
@@ -404,16 +404,22 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
 	return ret_val;
 }
 
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
 	return FPGA_FAIL;
 }
 
 /* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+	.load = virtex2_load,
+	.dump = virtex2_dump,
+	.info = virtex2_info,
+};
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index 2e0db535d4..8837f5c122 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -19,19 +19,8 @@
 #include <spartan3.h>
 #include <zynqpl.h>
 
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* Define FPGA_DEBUG to get debug printf's */
-#ifdef	FPGA_DEBUG
-#define	PRINTF(fmt,args...)	printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
 /* Local Static Functions */
-static int xilinx_validate (Xilinx_desc * desc, char *fn);
+static int xilinx_validate(xilinx_desc *desc, char *fn);
 
 /* ------------------------------------------------------------------------- */
 
@@ -43,7 +32,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
 	unsigned char *dataptr;
 	unsigned int i;
 	const fpga_desc *desc;
-	Xilinx_desc *xdesc;
+	xilinx_desc *xdesc;
 
 	dataptr = (unsigned char *)fpgadata;
 	/* Find out fpga_description */
@@ -94,7 +83,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
 			return FPGA_FAIL;
 		}
 	} else {
-		printf("%s: Please fill correct device ID to Xilinx_desc\n",
+		printf("%s: Please fill correct device ID to xilinx_desc\n",
 		       __func__);
 	}
 	printf("  part number = \"%s\"\n", buffer);
@@ -141,134 +130,40 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size)
 	return fpga_load(devnum, dataptr, swapsize);
 }
 
-int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
-	int ret_val = FPGA_FAIL;	/* assume a failure */
-
 	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
-	} else
-		switch (desc->family) {
-		case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
-			PRINTF ("%s: Launching the Spartan-II Loader...\n",
-					__FUNCTION__);
-			ret_val = Spartan2_load (desc, buf, bsize);
-#else
-			printf ("%s: No support for Spartan-II devices.\n",
-					__FUNCTION__);
-#endif
-			break;
-		case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
-			PRINTF ("%s: Launching the Spartan-III Loader...\n",
-					__FUNCTION__);
-			ret_val = Spartan3_load (desc, buf, bsize);
-#else
-			printf ("%s: No support for Spartan-III devices.\n",
-					__FUNCTION__);
-#endif
-			break;
-		case Xilinx_Virtex2:
-#if defined(CONFIG_FPGA_VIRTEX2)
-			PRINTF ("%s: Launching the Virtex-II Loader...\n",
-					__FUNCTION__);
-			ret_val = Virtex2_load (desc, buf, bsize);
-#else
-			printf ("%s: No support for Virtex-II devices.\n",
-					__FUNCTION__);
-#endif
-			break;
-		case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
-			PRINTF("%s: Launching the Zynq PL Loader...\n",
-			       __func__);
-			ret_val = zynq_load(desc, buf, bsize);
-#else
-			printf("%s: No support for Zynq devices.\n",
-			       __func__);
-#endif
-			break;
-
-		default:
-			printf ("%s: Unsupported family type, %d\n",
-					__FUNCTION__, desc->family);
-		}
+		return FPGA_FAIL;
+	}
 
-	return ret_val;
+	return desc->operations->load(desc, buf, bsize);
 }
 
-int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
-	int ret_val = FPGA_FAIL;	/* assume a failure */
-
 	if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
 		printf ("%s: Invalid device descriptor\n", __FUNCTION__);
-	} else
-		switch (desc->family) {
-		case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
-			PRINTF ("%s: Launching the Spartan-II Reader...\n",
-					__FUNCTION__);
-			ret_val = Spartan2_dump (desc, buf, bsize);
-#else
-			printf ("%s: No support for Spartan-II devices.\n",
-					__FUNCTION__);
-#endif
-			break;
-		case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
-			PRINTF ("%s: Launching the Spartan-III Reader...\n",
-					__FUNCTION__);
-			ret_val = Spartan3_dump (desc, buf, bsize);
-#else
-			printf ("%s: No support for Spartan-III devices.\n",
-					__FUNCTION__);
-#endif
-			break;
-		case Xilinx_Virtex2:
-#if defined( CONFIG_FPGA_VIRTEX2)
-			PRINTF ("%s: Launching the Virtex-II Reader...\n",
-					__FUNCTION__);
-			ret_val = Virtex2_dump (desc, buf, bsize);
-#else
-			printf ("%s: No support for Virtex-II devices.\n",
-					__FUNCTION__);
-#endif
-			break;
-		case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
-			PRINTF("%s: Launching the Zynq PL Reader...\n",
-			       __func__);
-			ret_val = zynq_dump(desc, buf, bsize);
-#else
-			printf("%s: No support for Zynq devices.\n",
-			       __func__);
-#endif
-			break;
-
-		default:
-			printf ("%s: Unsupported family type, %d\n",
-					__FUNCTION__, desc->family);
-		}
+		return FPGA_FAIL;
+	}
 
-	return ret_val;
+	return desc->operations->dump(desc, buf, bsize);
 }
 
-int xilinx_info (Xilinx_desc * desc)
+int xilinx_info(xilinx_desc *desc)
 {
 	int ret_val = FPGA_FAIL;
 
 	if (xilinx_validate (desc, (char *)__FUNCTION__)) {
 		printf ("Family:        \t");
 		switch (desc->family) {
-		case Xilinx_Spartan2:
+		case xilinx_spartan2:
 			printf ("Spartan-II\n");
 			break;
-		case Xilinx_Spartan3:
+		case xilinx_spartan3:
 			printf ("Spartan-III\n");
 			break;
-		case Xilinx_Virtex2:
+		case xilinx_virtex2:
 			printf ("Virtex-II\n");
 			break;
 		case xilinx_zynq:
@@ -315,47 +210,7 @@ int xilinx_info (Xilinx_desc * desc)
 
 		if (desc->iface_fns) {
 			printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
-			switch (desc->family) {
-			case Xilinx_Spartan2:
-#if defined(CONFIG_FPGA_SPARTAN2)
-				Spartan2_info (desc);
-#else
-				/* just in case */
-				printf ("%s: No support for Spartan-II devices.\n",
-						__FUNCTION__);
-#endif
-				break;
-			case Xilinx_Spartan3:
-#if defined(CONFIG_FPGA_SPARTAN3)
-				Spartan3_info (desc);
-#else
-				/* just in case */
-				printf ("%s: No support for Spartan-III devices.\n",
-						__FUNCTION__);
-#endif
-				break;
-			case Xilinx_Virtex2:
-#if defined(CONFIG_FPGA_VIRTEX2)
-				Virtex2_info (desc);
-#else
-				/* just in case */
-				printf ("%s: No support for Virtex-II devices.\n",
-						__FUNCTION__);
-#endif
-				break;
-			case xilinx_zynq:
-#if defined(CONFIG_FPGA_ZYNQPL)
-				zynq_info(desc);
-#else
-				/* just in case */
-				printf("%s: No support for Zynq devices.\n",
-				       __func__);
-#endif
-				/* Add new family types here */
-			default:
-				/* we don't need a message here - we give one up above */
-				;
-			}
+			desc->operations->info(desc);
 		} else
 			printf ("No Device Function Table.\n");
 
@@ -369,7 +224,7 @@ int xilinx_info (Xilinx_desc * desc)
 
 /* ------------------------------------------------------------------------- */
 
-static int xilinx_validate (Xilinx_desc * desc, char *fn)
+static int xilinx_validate(xilinx_desc *desc, char *fn)
 {
 	int ret_val = false;
 
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 923a1586d8..c066f21d79 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -36,7 +36,7 @@
 #define CONFIG_SYS_FPGA_PROG_TIME	(CONFIG_SYS_HZ * 4) /* 4 s */
 #endif
 
-int zynq_info(Xilinx_desc *desc)
+static int zynq_info(xilinx_desc *desc)
 {
 	return FPGA_SUCCESS;
 }
@@ -147,76 +147,57 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap)
 		}
 		/* Loop can be huge - support CTRL + C */
 		if (ctrlc())
-			return 0;
+			return NULL;
 	}
-	return 0;
+	return NULL;
 }
 
-
-int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
 {
-	unsigned long ts; /* Timestamp */
-	u32 partialbit = 0;
-	u32 i, control, isr_status, status, swap, diff;
-	u32 *buf_start;
-
-	/* Detect if we are going working with partial or full bitstream */
-	if (bsize != desc->size) {
-		printf("%s: Working with partial bitstream\n", __func__);
-		partialbit = 1;
-	}
+	unsigned long ts;
+	u32 isr_status;
 
-	buf_start = check_data((u8 *)buf, bsize, &swap);
-	if (!buf_start)
-		return FPGA_FAIL;
-
-	/* Check if data is postpone from start */
-	diff = (u32)buf_start - (u32)buf;
-	if (diff) {
-		printf("%s: Bitstream is not validated yet (diff %x)\n",
-		       __func__, diff);
-		return FPGA_FAIL;
-	}
+	/* Set up the transfer */
+	writel((u32)srcbuf, &devcfg_base->dma_src_addr);
+	writel(dstbuf, &devcfg_base->dma_dst_addr);
+	writel(srclen, &devcfg_base->dma_src_len);
+	writel(dstlen, &devcfg_base->dma_dst_len);
 
-	if ((u32)buf < SZ_1M) {
-		printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
-		       __func__, (u32)buf);
-		return FPGA_FAIL;
-	}
+	isr_status = readl(&devcfg_base->int_sts);
 
-	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
-		u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+	/* Polling the PCAP_INIT status for Set */
+	ts = get_timer(0);
+	while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
+		if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
+			debug("%s: Error: isr = 0x%08X\n", __func__,
+			      isr_status);
+			debug("%s: Write count = 0x%08X\n", __func__,
+			      readl(&devcfg_base->write_count));
+			debug("%s: Read count = 0x%08X\n", __func__,
+			      readl(&devcfg_base->read_count));
 
-		/*
-		 * This might be dangerous but permits to flash if
-		 * ARCH_DMA_MINALIGN is greater than header size
-		 */
-		if (new_buf > buf_start) {
-			debug("%s: Aligned buffer is after buffer start\n",
-			      __func__);
-			new_buf -= ARCH_DMA_MINALIGN;
+			return FPGA_FAIL;
 		}
+		if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
+			printf("%s: Timeout wait for DMA to complete\n",
+			       __func__);
+			return FPGA_FAIL;
+		}
+		isr_status = readl(&devcfg_base->int_sts);
+	}
 
-		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
-		       (u32)buf_start, (u32)new_buf, swap);
-
-		for (i = 0; i < (bsize/4); i++)
-			new_buf[i] = load_word(&buf_start[i], swap);
-
-		swap = SWAP_DONE;
-		buf = new_buf;
-	} else if (swap != SWAP_DONE) {
-		/* For bitstream which are aligned */
-		u32 *new_buf = (u32 *)buf;
+	debug("%s: DMA transfer is done\n", __func__);
 
-		printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
-		       swap);
+	/* Clear out the DMA status */
+	writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
 
-		for (i = 0; i < (bsize/4); i++)
-			new_buf[i] = load_word(&buf_start[i], swap);
+	return FPGA_SUCCESS;
+}
 
-		swap = SWAP_DONE;
-	}
+static int zynq_dma_xfer_init(u32 partialbit)
+{
+	u32 status, control, isr_status;
+	unsigned long ts;
 
 	/* Clear loopback bit */
 	clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
@@ -298,6 +279,101 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 		writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
 	}
 
+	return FPGA_SUCCESS;
+}
+
+static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
+{
+	u32 *new_buf;
+	u32 i;
+
+	if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
+		new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
+
+		/*
+		 * This might be dangerous but permits to flash if
+		 * ARCH_DMA_MINALIGN is greater than header size
+		 */
+		if (new_buf > buf) {
+			debug("%s: Aligned buffer is after buffer start\n",
+			      __func__);
+			new_buf -= ARCH_DMA_MINALIGN;
+		}
+		printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
+		       (u32)buf, (u32)new_buf, swap);
+
+		for (i = 0; i < (len/4); i++)
+			new_buf[i] = load_word(&buf[i], swap);
+
+		buf = new_buf;
+	} else if (swap != SWAP_DONE) {
+		/* For bitstream which are aligned */
+		u32 *new_buf = (u32 *)buf;
+
+		printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
+		       swap);
+
+		for (i = 0; i < (len/4); i++)
+			new_buf[i] = load_word(&buf[i], swap);
+	}
+
+	return buf;
+}
+
+static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
+				   size_t bsize, u32 blocksize, u32 *swap,
+				   u32 *partialbit)
+{
+	u32 *buf_start;
+	u32 diff;
+
+	/* Detect if we are going working with partial or full bitstream */
+	if (bsize != desc->size) {
+		printf("%s: Working with partial bitstream\n", __func__);
+		*partialbit = 1;
+	}
+	buf_start = check_data((u8 *)buf, blocksize, swap);
+
+	if (!buf_start)
+		return FPGA_FAIL;
+
+	/* Check if data is postpone from start */
+	diff = (u32)buf_start - (u32)buf;
+	if (diff) {
+		printf("%s: Bitstream is not validated yet (diff %x)\n",
+		       __func__, diff);
+		return FPGA_FAIL;
+	}
+
+	if ((u32)buf < SZ_1M) {
+		printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
+		       __func__, (u32)buf);
+		return FPGA_FAIL;
+	}
+
+	if (zynq_dma_xfer_init(*partialbit))
+		return FPGA_FAIL;
+
+	return 0;
+}
+
+
+static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize)
+{
+	unsigned long ts; /* Timestamp */
+	u32 partialbit = 0;
+	u32 isr_status, swap;
+
+	/*
+	 * send bsize inplace of blocksize as it was not a bitstream
+	 * in chunks
+	 */
+	if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
+				    &partialbit))
+		return FPGA_FAIL;
+
+	buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
+
 	debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
 	debug("%s: Size = %zu\n", __func__, bsize);
 
@@ -305,37 +381,10 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 	flush_dcache_range((u32)buf, (u32)buf +
 			   roundup(bsize, ARCH_DMA_MINALIGN));
 
-	/* Set up the transfer */
-	writel((u32)buf | 1, &devcfg_base->dma_src_addr);
-	writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
-	writel(bsize >> 2, &devcfg_base->dma_src_len);
-	writel(0, &devcfg_base->dma_dst_len);
+	if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
+		return FPGA_FAIL;
 
 	isr_status = readl(&devcfg_base->int_sts);
-
-	/* Polling the PCAP_INIT status for Set */
-	ts = get_timer(0);
-	while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
-		if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
-			debug("%s: Error: isr = 0x%08X\n", __func__,
-			      isr_status);
-			debug("%s: Write count = 0x%08X\n", __func__,
-			      readl(&devcfg_base->write_count));
-			debug("%s: Read count = 0x%08X\n", __func__,
-			      readl(&devcfg_base->read_count));
-
-			return FPGA_FAIL;
-		}
-		if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
-			printf("%s: Timeout wait for DMA to complete\n",
-			       __func__);
-			return FPGA_FAIL;
-		}
-		isr_status = readl(&devcfg_base->int_sts);
-	}
-
-	debug("%s: DMA transfer is done\n", __func__);
-
 	/* Check FPGA configuration completion */
 	ts = get_timer(0);
 	while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
@@ -349,16 +398,19 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 
 	debug("%s: FPGA config done\n", __func__);
 
-	/* Clear out the DMA status */
-	writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
-
 	if (!partialbit)
 		zynq_slcr_devcfg_enable();
 
 	return FPGA_SUCCESS;
 }
 
-int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
 	return FPGA_FAIL;
 }
+
+struct xilinx_fpga_op zynq_op = {
+	.load = zynq_load,
+	.dump = zynq_dump,
+	.info = zynq_info,
+};
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 90c8387918..5ba0e03862 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -216,21 +216,7 @@ static int twsi_stop(int status)
  */
 
 #define TWSI_FREQUENCY(m, n) \
-	((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))))
-
-/*
- * These are required to be reprogrammed before enabling the controller
- * because a reset loses them.
- * Default values come from the spec, but a twsi_reset will change them.
- * twsi_slave_address left uninitialized lest checkpatch.pl complains.
- */
-
-/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */
-static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */
-/* Default frequency corresponding to default m=4, n=4 */
-static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4);
-/* Default slave address is 0 (so is an uninitialized static) */
-static u8 twsi_slave_address;
+	(CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
 
 /*
  * Reset controller.
@@ -238,7 +224,7 @@ static u8 twsi_slave_address;
  * Controller reset also resets the baud rate and slave address, so
  * re-establish them.
  */
-static void twsi_reset(void)
+static void twsi_reset(u8 baud_rate, u8 slave_address)
 {
 	/* ensure controller will be enabled by any twsi*() function */
 	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
@@ -247,9 +233,9 @@ static void twsi_reset(void)
 	/* wait 2 ms -- this is what the Marvell LSP does */
 	udelay(20000);
 	/* set baud rate */
-	writel(twsi_baud_rate, &twsi->baudrate);
+	writel(baud_rate, &twsi->baudrate);
 	/* set slave address even though we don't use it */
-	writel(twsi_slave_address, &twsi->slave_address);
+	writel(slave_address, &twsi->slave_address);
 	writel(0, &twsi->xtnd_slave_addr);
 	/* assert STOP but don't care for the result */
 	(void) twsi_stop(0);
@@ -277,12 +263,8 @@ void i2c_init(int requested_speed, int slaveadd)
 			}
 		}
 	}
-	/* save baud rate and slave for later calls to twsi_reset */
-	twsi_baud_rate = baud;
-	twsi_actual_speed = highest_speed;
-	twsi_slave_address = slaveadd;
 	/* reset controller */
-	twsi_reset();
+	twsi_reset(baud, slaveadd);
 }
 
 /*
diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c
index f1f65131a2..b3264af452 100644
--- a/drivers/i2c/zynq_i2c.c
+++ b/drivers/i2c/zynq_i2c.c
@@ -142,7 +142,7 @@ static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask)
 			break;
 	}
 #ifdef DEBUG
-	zynq_i2c_debug_status(zynq_i2c));
+	zynq_i2c_debug_status(zynq_i2c);
 #endif
 	/* Clear interrupt status flags */
 	writel(int_status & mask, &zynq_i2c->interrupt_status);
@@ -235,7 +235,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 	clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD);
 
 #ifdef DEBUG
-	zynq_i2c_debug_status();
+	zynq_i2c_debug_status(zynq_i2c);
 #endif
 	return 0;
 }
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 4c3b93d413..50cba64d99 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 	else if (cmd->resp_type & MMC_RSP_PRESENT)
 		xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
 		xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index c45593bcc0..78751b2600 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -390,6 +390,8 @@ static int dw_phy_init(struct eth_device *dev)
 	if (!phydev)
 		return -1;
 
+	phy_connect_dev(phydev, dev);
+
 	phydev->supported &= PHY_GBIT_FEATURES;
 	phydev->advertising = phydev->supported;
 
diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
index b68d808c74..4de9d41642 100644
--- a/drivers/net/dm9000x.c
+++ b/drivers/net/dm9000x.c
@@ -345,7 +345,7 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
 	if (!is_valid_ether_addr(dev->enetaddr)) {
 #ifdef CONFIG_RANDOM_MACADDR
 		printf("Bad MAC address (uninitialized EEPROM?), randomizing\n");
-		eth_random_enetaddr(dev->enetaddr);
+		eth_random_addr(dev->enetaddr);
 		printf("MAC: %pM\n", dev->enetaddr);
 #else
 		printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n");
diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile
index ee5d768937..5ae3b167a9 100644
--- a/drivers/net/fm/Makefile
+++ b/drivers/net/fm/Makefile
@@ -32,5 +32,6 @@ obj-$(CONFIG_PPC_T2080) += t2080.o
 obj-$(CONFIG_PPC_T2081) += t2080.o
 obj-$(CONFIG_PPC_T4240) += t4240.o
 obj-$(CONFIG_PPC_T4160) += t4240.o
+obj-$(CONFIG_PPC_T4080) += t4240.o
 obj-$(CONFIG_PPC_B4420) += b4860.o
 obj-$(CONFIG_PPC_B4860) += b4860.o
diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
index 2f4bc11a6c..de9c0e9cd2 100644
--- a/drivers/net/fm/memac_phy.c
+++ b/drivers/net/fm/memac_phy.c
@@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
 		clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-	} else {
+	} else
 		setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-		setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
-	}
 
 	/* Wait till the bus is free */
 	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
@@ -76,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 		c45 = 0; /* clause 22 */
 		dev_addr = regnum & 0x1f;
 		clrbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-	} else {
+	} else
 		setbits_be32(&regs->mdio_stat, MDIO_STAT_ENC);
-		setbits_be32(&regs->mdio_stat, MDIO_STAT_HOLD_15_CLK);
-	}
 
 	/* Wait till the bus is free */
 	while ((in_be32(&regs->mdio_stat)) & MDIO_STAT_BSY)
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
index 8eee272cf1..98c4f09629 100644
--- a/drivers/net/ftmac110.c
+++ b/drivers/net/ftmac110.c
@@ -425,7 +425,7 @@ int ftmac110_initialize(bd_t *bis)
 	dev->recv = ftmac110_recv;
 
 	if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr))
-		eth_random_enetaddr(dev->enetaddr);
+		eth_random_addr(dev->enetaddr);
 
 	/* allocate tx descriptors (it must be 16 bytes aligned) */
 	chip->txd = dma_alloc_coherent(
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index abd4e5b463..d509e30d35 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -31,9 +31,7 @@ static int ar8035_config(struct phy_device *phydev)
 	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100));
 
-	genphy_config_aneg(phydev);
-
-	phy_reset(phydev);
+	phydev->supported = phydev->drv->features;
 
 	return 0;
 }
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c691fbbbc6..230ed97dd1 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -18,6 +18,7 @@
 #include <phy.h>
 #include <errno.h>
 #include <linux/err.h>
+#include <linux/compiler.h>
 
 /* Generic PHY support and helper functions */
 
@@ -577,7 +578,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
  * Description: Reads the ID registers of the PHY at @addr on the
  *   @bus, stores it in @phy_id and returns zero on success.
  */
-static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
+int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
 {
 	int phy_reg;
 
diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c
index 3a55d271a5..c58fe50b72 100644
--- a/drivers/net/phy/vitesse.c
+++ b/drivers/net/phy/vitesse.c
@@ -58,6 +58,14 @@
 #define MIIM_VSC8514_18G_QSGMII		0x80e0
 #define MIIM_VSC8514_18G_CMDSTAT	0x8000
 
+/* Vitesse VSC8664 Control/Status Register */
+#define MIIM_VSC8664_SERDES_AND_SIGDET	0x13
+#define MIIM_VSC8664_ADDITIONAL_DEV	0x16
+#define MIIM_VSC8664_EPHY_CON		0x17
+#define MIIM_VSC8664_LED_CON		0x1E
+
+#define PHY_EXT_PAGE_ACCESS_EXTENDED	0x0001
+
 /* CIS8201 */
 static int vitesse_config(struct phy_device *phydev)
 {
@@ -244,6 +252,33 @@ static int vsc8514_config(struct phy_device *phydev)
 	return 0;
 }
 
+static int vsc8664_config(struct phy_device *phydev)
+{
+	u32 val;
+
+	/* Enable MAC interface auto-negotiation */
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON);
+	val |= (1 << 13);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
+		  PHY_EXT_PAGE_ACCESS_EXTENDED);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET);
+	val |= (1 << 11);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val);
+	phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
+
+	/* Enable LED blink */
+	val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON);
+	val &= ~(1 << 2);
+	phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val);
+
+	genphy_config_aneg(phydev);
+
+	return 0;
+}
+
 static struct phy_driver VSC8211_driver = {
 	.name	= "Vitesse VSC8211",
 	.uid	= 0xfc4b0,
@@ -334,6 +369,16 @@ static struct phy_driver VSC8662_driver = {
 	.shutdown = &genphy_shutdown,
 };
 
+static struct phy_driver VSC8664_driver = {
+	.name = "Vitesse VSC8664",
+	.uid = 0x70660,
+	.mask = 0xffff0,
+	.features = PHY_GBIT_FEATURES,
+	.config = &vsc8664_config,
+	.startup = &vitesse_startup,
+	.shutdown = &genphy_shutdown,
+};
+
 /* Vitesse bought Cicada, so we'll put these here */
 static struct phy_driver cis8201_driver = {
 	.name = "CIS8201",
@@ -366,6 +411,7 @@ int phy_vitesse_init(void)
 	phy_register(&VSC8574_driver);
 	phy_register(&VSC8514_driver);
 	phy_register(&VSC8662_driver);
+	phy_register(&VSC8664_driver);
 	phy_register(&cis8201_driver);
 	phy_register(&cis8204_driver);
 
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 6317fb1324..3a41b0ec17 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -49,8 +49,13 @@ static void set_inbound_window(volatile pit_t *pi,
 				u64 size)
 {
 	u32 sz = (__ilog2_u64(size) - 1);
-	u32 flag = PIWAR_EN | PIWAR_LOCAL |
-			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+	u32 flag = 0;
+#else
+	u32 flag = PIWAR_LOCAL;
+#endif
+
+	flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
 
 	out_be32(&pi->pitar, r->phys_start >> 12);
 	out_be32(&pi->piwbar, r->bus_start >> 12);
diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c
index 704c2439b1..d29d969533 100644
--- a/drivers/power/tps6586x.c
+++ b/drivers/power/tps6586x.c
@@ -32,7 +32,7 @@ enum {
 };
 
 #define MAX_I2C_RETRY	3
-int tps6586x_read(int reg)
+static int tps6586x_read(int reg)
 {
 	int	i;
 	uchar	data;
@@ -61,7 +61,7 @@ exit:
 	return retval;
 }
 
-int tps6586x_write(int reg, uchar *data, uint len)
+static int tps6586x_write(int reg, uchar *data, uint len)
 {
 	int	i;
 	int	retval = -1;
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index b1da75ec4d..9c5fbd1d69 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -14,6 +14,8 @@
 #include "asm/immap_qe.h"
 #include "qe.h"
 
+#define MPC85xx_DEVDISR_QE_DISABLE	0x1
+
 qe_map_t		*qe_immr = NULL;
 static qe_snum_t	snums[QE_NUM_OF_SNUM];
 
@@ -317,7 +319,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 	size_t calc_size = sizeof(struct qe_firmware);
 	size_t length;
 	const struct qe_header *hdr;
-
+#ifdef CONFIG_DEEP_SLEEP
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
 	if (!firmware) {
 		printf("Invalid address\n");
 		return -EINVAL;
@@ -330,6 +334,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
 	    (hdr->magic[2] != 'F')) {
 		printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
 		return -EPERM;
 	}
 
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8a13454943..f26979dbe1 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -33,6 +33,12 @@
 #if defined(CONFIG_K2HK_EVM)
 #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE   0
 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0))
+#undef UART_MCRVAL
+#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL
+#define UART_MCRVAL             (UART_MCR_RTS | UART_MCR_AFE)
+#else
+#define UART_MCRVAL             (UART_MCR_RTS)
+#endif
 #endif
 
 #ifndef CONFIG_SYS_NS16550_IER
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index c4fb59cfb3..fd61a5e545 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -74,9 +74,6 @@ static int on_baudrate(const char *name, const char *value, enum env_op op,
 		}
 
 		gd->baudrate = baudrate;
-#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2)
-		gd->bd->bi_baudrate = baudrate;
-#endif
 
 		serial_setbrg();
 
@@ -502,12 +499,11 @@ int uart_post_test(int flags)
 	unsigned char c;
 	int ret, saved_baud, b;
 	struct serial_device *saved_dev, *s;
-	bd_t *bd = gd->bd;
 
 	/* Save current serial state */
 	ret = 0;
 	saved_dev = serial_current;
-	saved_baud = bd->bi_baudrate;
+	saved_baud = gd->baudrate;
 
 	for (s = serial_devices; s; s = s->next) {
 		/* If this driver doesn't support loop back, skip it */
@@ -530,7 +526,7 @@ int uart_post_test(int flags)
 
 		/* Test every available baud rate */
 		for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
-			bd->bi_baudrate = bauds[b];
+			gd->baudrate = bauds[b];
 			serial_setbrg();
 
 			/*
@@ -572,7 +568,7 @@ int uart_post_test(int flags)
  done:
 	/* Restore previous serial state */
 	serial_current = saved_dev;
-	bd->bi_baudrate = saved_baud;
+	gd->baudrate = saved_baud;
 	serial_reinit_all();
 	serial_setbrg();
 
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 6cb4d98668..45062e699b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -104,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	if (!strncmp(phy_type, "utmi", 4)) {
 #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
-		setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI);
-		setbits_be32(&ehci->control, UTMI_PHY_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				PHY_CLK_SEL_UTMI);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				UTMI_PHY_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
 #endif
 		out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
-		setbits_be32(&ehci->control, USB_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				USB_EN);
 	} else {
-		setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
-		clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
+		clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
+				PHY_CLK_SEL_ULPI);
+		clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
+				CONTROL_REGISTER_W1C_MASK, USB_EN);
 		udelay(1000); /* delay required for PHY Clk to appear */
 		if (!usb_phy_clk_valid(ehci))
 			return -EINVAL;
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 853303b5e5..bb4d7d8c14 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -128,12 +128,12 @@ void lcd_ctrl_init(void *lcdbase)
 	value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1);
 	lcdc_writel(&regs->lcdc_lcdcfg1, value);
 
-	value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin);
-	value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1);
+	value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin);
+	value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1);
 	lcdc_writel(&regs->lcdc_lcdcfg2, value);
 
-	value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1);
-	value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1);
+	value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1);
+	value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1);
 	lcdc_writel(&regs->lcdc_lcdcfg3, value);
 
 	/* Display size */
diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c
index 3e21fb2306..f75d77064e 100644
--- a/drivers/video/mxc_ipuv3_fb.c
+++ b/drivers/video/mxc_ipuv3_fb.c
@@ -13,6 +13,7 @@
 
 #include <common.h>
 #include <asm/errno.h>
+#include <asm/global_data.h>
 #include <linux/string.h>
 #include <linux/list.h>
 #include <linux/fb.h>
@@ -24,6 +25,8 @@
 #include "mxcfb.h"
 #include "ipu_regs.h"
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static int mxcfb_map_video_memory(struct fb_info *fbi);
 static int mxcfb_unmap_video_memory(struct fb_info *fbi);
 
@@ -415,6 +418,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi)
 
 	fbi->screen_size = fbi->fix.smem_len;
 
+	gd->fb_base = fbi->fix.smem_start;
+
 	/* Clear the screen */
 	memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);