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authorYork Sun <yorksun@freescale.com>2015-11-04 10:03:22 -0800
committerYork Sun <yorksun@freescale.com>2015-12-13 18:27:28 -0800
commitc4243ac9e2713897a63dcdc3a96bf088fdb49866 (patch)
treeff5766eef6dc2f238791a238bccbc484941373cc /board
parent6c6e006a2083f2da7b4f66c6bb82ce8b3fb713a3 (diff)
armv8/ls2080aqds: Update DDR settings for four chip-select case
When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'board')
-rw-r--r--board/freescale/ls2080aqds/ddr.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c
index ae681de35e..7e67ee0335 100644
--- a/board/freescale/ls2080aqds/ddr.c
+++ b/board/freescale/ls2080aqds/ddr.c
@@ -134,10 +134,18 @@ found:
popts->zq_en = 1;
if (ddr_freq < 2350) {
- popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
- popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
+ if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+ /* four chip-selects */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+ popts->twot_en = 1; /* enable 2T timing */
+ } else {
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+ }
} else {
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);