diff options
| author | Hans de Goede <hdegoede@redhat.com> | 2015-08-15 13:17:49 +0200 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-08-31 08:43:42 +0200 |
| commit | 022a99d8b2f84e6bda44e6dcfd1748219b665143 (patch) | |
| tree | 25adf4c6ac41f656b2bf935a572afbed2764c3bf /board/sunxi/board.c | |
| parent | 008ac1dfe0815476cca819c16e06616c12c303b7 (diff) | |
sunxi_nand_spl: Add support for sun4i and sun5i SoCs
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.
Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'board/sunxi/board.c')
| -rw-r--r-- | board/sunxi/board.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 1ebd0a423d..d411e96c76 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -112,13 +112,19 @@ int dram_init(void) static void nand_pinmux_setup(void) { unsigned int pin; - for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) - sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); - for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(22); pin++) + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++) sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I + for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++) + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND); +#endif + /* sun4i / sun7i do have a PC23, but it is not used for nand, + * only sun7i has a PC24 */ +#ifdef CONFIG_MACH_SUN7I sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND); +#endif } static void nand_clock_setup(void) |