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authorAnatolij Gustschin <agust@denx.de>2008-11-13 18:08:57 +0100
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-12-03 22:47:01 -0600
commitdd332e18d082de75eca3fc2c7c778f5d4571a096 (patch)
tree94b5fe6ea33556610852de749ffb9ccb8450511c /board/socrates
parenta2cd50ed6ef0ac6b127b3d6db756979a8336718d (diff)
85xx: socrates: fix DDR SDRAM tlb entry configuration
since commit be0bd8234b9777ecd63c4c686f72af070d886517 tlb entry for socrates DDR SDRAM will be reconfigured by setup_ddr_tlbs() from initdram() causing an inconsistency with previously configured DDR SDRAM tlb entry from tlb_table: socrates>l2cam 7 9 IDX PID EPN SIZE V TS RPN U0-U3 WIMGE UUUSSS 7 : 00 00000000 256MB V 0 -> 0_00000000 0000 -I-G- ---RWX 8 : 00 00000000 256MB V 0 -> 0_00000000 0000 ----- ---RWX 9 : 00 10000000 256MB V 0 -> 0_10000000 0000 ----- ---RWX This patch makes the presence of the DDR SDRAM tlb entry in the tlb_table dependent on CONFIG_SPD_EEPROM to avoid this inconsistency. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board/socrates')
-rw-r--r--board/socrates/tlb.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index b91b1eab6e..4591e466b9 100644
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -100,6 +100,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
+#if !defined(CONFIG_SPD_EEPROM)
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
@@ -114,6 +115,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);