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| author | Wolfgang Denk <wd@atlas.denx.de> | 2006-03-06 23:18:48 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@atlas.denx.de> | 2006-03-06 23:18:48 +0100 |
| commit | 951a954b77ef30df1f5c1b7b9b4312e783b2cbb4 (patch) | |
| tree | 8f94ab1a2e15fbf31c322e6be1f750e10ac2fe2f /board/mcc200/mt48lc8m32b2-6-7.h | |
| parent | ac7d97dcbb499c96c8182757f301dd2e09c9f49d (diff) | |
| parent | bfc81252c0de3bfcf92c7c35bc04341fb33e4e4e (diff) | |
Merge with /home/wd/git/u-boot/master
Code cleanup.
Diffstat (limited to 'board/mcc200/mt48lc8m32b2-6-7.h')
| -rw-r--r-- | board/mcc200/mt48lc8m32b2-6-7.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/board/mcc200/mt48lc8m32b2-6-7.h b/board/mcc200/mt48lc8m32b2-6-7.h new file mode 100644 index 0000000000..13aebbd8af --- /dev/null +++ b/board/mcc200/mt48lc8m32b2-6-7.h @@ -0,0 +1,12 @@ +/* + * Configuration Registers for the MT48LC8M32B2 SDRAM on the MPC5200 platform + */ + +#define SDRAM_DDR 0 /* is SDR */ + +/* Settings for XLB = 132 MHz */ + +#define SDRAM_MODE 0x008d0000 /* CL-3 BURST-8 -> Mode Register MBAR + 0x0100 */ +#define SDRAM_CONTROL 0x504f0000 /* Control Register MBAR + 0x0104 */ +#define SDRAM_CONFIG1 0xc2222900 /* Delays between commands -> Configuration Register 1 MBAR + 0x0108 */ +#define SDRAM_CONFIG2 0x88c70000 /* Delays between commands -> Configuration Register 2 MBAR + 0x010C */ |