board/p1_p2_rdb:Enable p1_p2_rdb boot from NAND/SD/SPI in SPL

In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

1 files changed, 5 insertions, 11 deletions

diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 17d3beac39..98ee5f1021 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -180,27 +180,22 @@ fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
 
 phys_size_t fixed_sdram (void)
 {
-	char buf[32];
 	fsl_ddr_cfg_regs_t ddr_cfg_regs;
 	size_t ddr_size;
 	struct cpu_type *cpu;
 	ulong ddr_freq, ddr_freq_mhz;
 
 	cpu = gd->arch.cpu;
-	/* P1020 and it's derivatives support max 32bit DDR width */
-	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
-		ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
-	} else {
-		ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	}
+
+	ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+
 #if defined(CONFIG_SYS_RAMBOOT)
 	return ddr_size;
 #endif
 	ddr_freq = get_ddr_freq(0);
 	ddr_freq_mhz = ddr_freq / 1000000;
 
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
+	printf("Configuring DDR for %ld T/s data rate\n", ddr_freq);
 
 	if(ddr_freq_mhz <= 400)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
@@ -211,8 +206,7 @@ phys_size_t fixed_sdram (void)
 	else if(ddr_freq_mhz <= 800)
 		memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
 	else
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-					strmhz(buf, ddr_freq));
+		panic("Unsupported DDR data rate %ld T/s\n", ddr_freq);
 
 	/* P1020 and it's derivatives support max 32bit DDR width */
 	if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {