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authorYangbo Lu <yangbo.lu@nxp.com>2016-02-16 10:54:41 +0800
committerYork Sun <york.sun@nxp.com>2016-03-21 12:42:14 -0700
commite477f4bdd40496a53f7c2c4290ef4ba16ca4d869 (patch)
tree64172924faeae79833f56ff6012c3253130cb56d /arch
parent0f4b82a555a3b4eab2febf06eedf51ad85ba8ddd (diff)
armv8/fsl-lsch2: fix sdhc clock frequency value
The eSDHC could select to use platform clock or peripheral clock to generate SD clock. The default selection is platform clock. So, fix the clock frequency value that's calculated for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 6f6a588292..453a93d94c 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -106,9 +106,13 @@ void get_sys_info(struct sys_info *sys_info)
#define HWA_CGA_M2_CLK_SEL 0x00000007
#define HWA_CGA_M2_CLK_SHIFT 0
#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
rcw_tmp = in_be32(&gur->rcwsr[15]);
rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#else
+ sys_info->freq_sdhc = sys_info->freq_systembus;
+#endif
#endif
#if defined(CONFIG_FSL_IFC)