Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx:
  powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND
  arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/ddr/options.c: Fix GCC 4.6 build warning
  drivers/qe/uec.c: Fix GCC 4.6 build warning
  drivers/usb/host/ehci-fsl.c: Fix GCC 4.6 build warning
  drivers/net/fm/fm.c: Fix GCC 4.6 build warning
  board/sbc8560/sbc8560.c: Fix GCC 4.6 build warning
  board/sbc8548/sbc8548.c: Fix GCC 4.6 build warning
  board/freescale/mpc8569mds/mpc8569mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8568mds/mpc8568mds.c: Fix GCC 4.6 build warning
  board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warning
  board/freescale/common/pixis.c: Fix GCC 4.6 build warning
  board/freescale/common/cds_pci_ft.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc8xxx/fsl_lbc.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/tlb.c: Fix GCC 4.6 build warning
  arch/powerpc/cpu/mpc85xx/cpu_init.c: Fix GCC 4.6 build warning
  phylib: Enable AR8021 phy support
  powerpc/85xx: Set max alloc length to 10MB on P1022DS
  powerpc/mpc85xx: Set SYSCLK to the required frequency
  powerpc/85xx: Fix NAND SPL support
  powerpc/85xx: Fix MPC8572DS NAND build
  fsl_ifc: Fixed a bug in the erratum handling code for IFC_A003399
  powerpc/85xx: Add support for Book-E MMU Arch v2.0
  powerpc/85xx: Make inclusion of USB device fixup conditional
  powerpc/85xx: Fix warning for USB device-fixup
  powerpc/85xx: resize the boot page TLB before relocating CCSR
  powerpc/85xx: verify the current address of CCSR before relocating it
  powerpc/85xx: add some missing sync instructions in the CCSR relocation code
  powerpc/85xx: fix some comments in the CCSR relocation code
  powerpc/85xx: fix definition of MAS register macros
  powerpc/mpc8548cds: Fix network initialization
  powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129
  powerpc/QorIQ: fix network frame manager TBI PHY address settings

13 files changed, 138 insertions, 37 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index a09eb91406..253bf08b6a 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -103,6 +103,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 	puts("Work-around for Erratum NMG_LBC103 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 0a4ce538f3..b9a8193759 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -317,7 +317,6 @@ int cpu_init_r(void)
 	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
 	uint svr, ver;
-	uint l2srbar;
 	u32 l2siz_field;
 
 	svr = get_svr();
@@ -385,8 +384,8 @@ int cpu_init_r(void)
 
 	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 		puts("already enabled");
-		l2srbar = l2cache->l2srbar0;
 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
+		u32 l2srbar = l2cache->l2srbar0;
 		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
 			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 4ef3c9a8a5..091af7c95a 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -71,7 +71,7 @@ void cpu_init_early_f(void)
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_IFC_A003399) && !defined(CONFIG_SYS_RAMBOOT)
 	ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-	u32  *l2srbar, *dst, *src;
+	u32  *dst, *src;
 	void (*setup_ifc_sram)(void);
 #endif
 
@@ -137,7 +137,7 @@ void cpu_init_early_f(void)
 	dst = (u32 *) SRAM_BASE_ADDR;
 	src = (u32 *) setup_ifc;
 	for (i = 0; i < 1024; i++)
-		*l2srbar++ = *src++;
+		*dst++ = *src++;
 
 	setup_ifc_sram();
 
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 89ed5b47fc..4b52dad56c 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -495,7 +495,6 @@ void fsl_serdes_init(void)
 	int cfg;
 	serdes_corenet_t *srds_regs;
 	int lane, bank, idx;
-	enum srds_prtcl lane_prtcl;
 	int have_bank[SRDS_MAX_BANK] = {};
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	u32 serdes8_devdisr = 0;
@@ -507,6 +506,7 @@ void fsl_serdes_init(void)
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
 	int need_serdes_a001;	/* TRUE == need work-around for SERDES A001 */
 #endif
+#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
 
@@ -516,6 +516,7 @@ void fsl_serdes_init(void)
 	 */
 	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 		buf = buffer;
+#endif
 
 	/* Is serdes enabled at all? */
 	if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
@@ -617,7 +618,10 @@ void fsl_serdes_init(void)
 		}
 	}
 
+#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl;
+
 		idx = serdes_get_lane_idx(lane);
 		lane_prtcl = serdes_get_prtcl(cfg, lane);
 
@@ -729,6 +733,7 @@ void fsl_serdes_init(void)
 
 #endif
 	}
+#endif
 
 #ifdef DEBUG
 	puts("\n");
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 5e0d78d006..7bd5cc0b0f 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -319,6 +319,55 @@ l2_disabled:
 #endif /* CONFIG_MPC8569 */
 
 /*
+ * Search for the TLB that covers the code we're executing, and shrink it
+ * so that it covers only this 4K page.  That will ensure that any other
+ * TLB we create won't interfere with it.  We assume that the TLB exists,
+ * which is why we don't check the Valid bit of MAS1.
+ *
+ * This is necessary, for example, when booting from the on-chip ROM,
+ * which (oddly) creates a single 4GB TLB that covers CCSR and DDR.
+ * If we don't shrink this TLB now, then we'll accidentally delete it
+ * in "purge_old_ccsr_tlb" below.
+ */
+	bl	nexti		/* Find our address */
+nexti:	mflr	r1		/* R1 = our PC */
+	li	r2, 0
+	mtspr	MAS6, r2	/* Assume the current PID and AS are 0 */
+	isync
+	msync
+	tlbsx	0, r1		/* This must succeed */
+
+	/* Set the size of the TLB to 4KB */
+	mfspr	r3, MAS1
+	li	r2, 0xF00
+	andc	r3, r3, r2	/* Clear the TSIZE bits */
+	ori	r3, r3, MAS1_TSIZE(BOOKE_PAGESZ_4K)@l
+	mtspr	MAS1, r3
+
+	/*
+	 * Set the base address of the TLB to our PC.  We assume that
+	 * virtual == physical.  We also assume that MAS2_EPN == MAS3_RPN.
+	 */
+	lis	r3, MAS2_EPN@h
+	ori	r3, r3, MAS2_EPN@l	/* R3 = MAS2_EPN */
+
+	and	r1, r1, r3	/* Our PC, rounded down to the nearest page */
+
+	mfspr	r2, MAS2
+	andc	r2, r2, r3
+	or	r2, r2, r1
+	mtspr	MAS2, r2	/* Set the EPN to our PC base address */
+
+	mfspr	r2, MAS3
+	andc	r2, r2, r3
+	or	r2, r2, r1
+	mtspr	MAS3, r2	/* Set the RPN to our PC base address */
+
+	isync
+	msync
+	tlbwe
+
+/*
  * Relocate CCSR, if necessary.  We relocate CCSR if (obviously) the default
  * location is not where we want it.  This typically happens on a 36-bit
  * system, where we want to move CCSR to near the top of 36-bit address space.
@@ -352,6 +401,8 @@ purge_old_ccsr_tlb:
 
 	li	r1, 0
 	mtspr	MAS6, r1	/* Search the current address space and PID */
+	isync
+	msync
 	tlbsx	0, r8
 	mfspr	r1, MAS1
 	andis.  r2, r1, MAS1_VALID@h	/* Check for the Valid bit */
@@ -359,6 +410,8 @@ purge_old_ccsr_tlb:
 
 	rlwinm	r1, r1, 0, 1, 31	/* Clear Valid bit */
 	mtspr	MAS1, r1
+	isync
+	msync
 	tlbwe
 1:
 
@@ -387,7 +440,7 @@ create_ccsr_new_tlb:
 	tlbwe
 
 	/*
-	 * Create a TLB for the old location of CCSR.  Register R9 is reserved
+	 * Create a TLB for the current location of CCSR.  Register R9 is reserved
 	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
 	 */
 create_ccsr_old_tlb:
@@ -407,6 +460,33 @@ create_ccsr_old_tlb:
 	msync
 	tlbwe
 
+	/*
+	 * We have a TLB for what we think is the current (old) CCSR.  Let's
+	 * verify that, otherwise we won't be able to move it.
+	 * CONFIG_SYS_CCSRBAR_DEFAULT is always a 32-bit number, so we only
+	 * need to compare the lower 32 bits of CCSRBAR on CoreNet systems.
+	 */
+verify_old_ccsr:
+	lis     r0, CONFIG_SYS_CCSRBAR_DEFAULT@h
+	ori     r0, r0, CONFIG_SYS_CCSRBAR_DEFAULT@l
+#ifdef CONFIG_FSL_CORENET
+	lwz	r1, 4(r9)		/* CCSRBARL */
+#else
+	lwz	r1, 0(r9)		/* CCSRBAR, shifted right by 12 */
+	slwi	r1, r1, 12
+#endif
+
+	cmpl	0, r0, r1
+
+	/*
+	 * If the value we read from CCSRBARL is not what we expect, then
+	 * enter an infinite loop.  This will at least allow a debugger to
+	 * halt execution and examine TLBs, etc.  There's no point in going
+	 * on.
+	 */
+infinite_debug_loop:
+	bne	infinite_debug_loop
+
 #ifdef CONFIG_FSL_CORENET
 
 #define CCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
@@ -446,7 +526,7 @@ create_temp_law:
 	 */
 read_old_ccsrbar:
 	lwz	r0, 0(r9)	/* CCSRBARH */
-	lwz	r0, 4(r9)	/* CCSRBARH */
+	lwz	r0, 4(r9)	/* CCSRBARL */
 	isync
 
 	/*
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 01a3561fa0..929f6a607e 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -172,7 +172,7 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
 
 void disable_tlb(u8 esel)
 {
-	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
+	u32 _mas0, _mas1, _mas2, _mas3;
 
 	free_tlb_cam(esel);
 
@@ -180,14 +180,13 @@ void disable_tlb(u8 esel)
 	_mas1 = 0;
 	_mas2 = 0;
 	_mas3 = 0;
-	_mas7 = 0;
 
 	mtspr(MAS0, _mas0);
 	mtspr(MAS1, _mas1);
 	mtspr(MAS2, _mas2);
 	mtspr(MAS3, _mas3);
 #ifdef CONFIG_ENABLE_36BIT_PHYS
-	mtspr(MAS7, _mas7);
+	mtspr(MAS7, 0);
 #endif
 	asm volatile("isync;msync;tlbwe;isync");
 
@@ -252,16 +251,20 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 	unsigned int tlb_size;
 	unsigned int wimge = 0;
 	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
-	unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+	unsigned int max_cam;
 	u64 size, memsize = (u64)memsize_in_meg << 20;
 
 #ifdef CONFIG_SYS_PPC_DDR_WIMGE
 	wimge = CONFIG_SYS_PPC_DDR_WIMGE;
 #endif
 	size = min(memsize, CONFIG_MAX_MEM_MAPPED);
-
-	/* Convert (4^max) kB to (2^max) bytes */
-	max_cam = max_cam * 2 + 10;
+	if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
+		/* Convert (4^max) kB to (2^max) bytes */
+		max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
+	} else {
+		/* Convert (2^max) kB to (2^max) bytes */
+		max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
+	}
 
 	for (i = 0; size && i < 8; i++) {
 		int ram_tlb_index = find_free_tlbcam();
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 15cd375ae3..2067d53ad2 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -672,7 +672,6 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		rcw_en = 1;
 		ap_en = popts->ap_en;
 	} else {
-		rcw_en = 0;
 		ap_en = 0;
 	}
 
@@ -702,9 +701,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((obc_cfg & 0x1) << 6)
 		| ((ap_en & 0x1) << 5)
 		| ((d_init & 0x1) << 4)
-#ifdef CONFIG_FSL_DDR3
 		| ((rcw_en & 0x1) << 2)
-#endif
 		| ((md_en & 0x1) << 0)
 		);
 	debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
@@ -745,7 +742,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
 
 #ifdef CONFIG_FSL_DDR3
 	if (unq_mrs_en) {	/* unique mode registers are supported */
-		for (i = 1; i < 4; i++) {
+		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 			if (popts->rtt_override)
 				rtt_wr = popts->rtt_wr_override_value;
 			else
@@ -944,7 +941,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 	debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
 
 	if (unq_mrs_en) {	/* unique mode registers are supported */
-		for (i = 1; i < 4; i++) {
+		for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 			if (popts->rtt_override)
 				rtt = popts->rtt_override_value;
 			else
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 4dc748b951..00ec57be1f 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -483,7 +483,9 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	unsigned int i;
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
+#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 	const struct dynamic_odt *pdodt = odt_unknown;
+#endif
 	ulong ddr_freq;
 
 	/*
@@ -493,6 +495,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
 		buf = buffer;
 
+#if defined(CONFIG_FSL_DDR3) || defined(CONFIG_FSL_DDR2)
 	/* Chip select options. */
 	if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
 		switch (pdimm[0].n_ranks) {
@@ -546,6 +549,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 			break;
 		}
 	}
+#endif
 
 	/* Pick chip-select local options. */
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 112c603532..d07ae1b4fe 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -87,13 +87,12 @@ void ft_fixup_num_cores(void *blob) {
 #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
-				const char *phy_type)
+static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
+				const char *phy_type, int start_offset)
 {
 	const char *compat = "fsl-usb2-dr";
 	const char *prop_mode = "dr_mode";
 	const char *prop_type = "phy_type";
-	static int start_offset = -1;
 	int node_offset;
 	int err;
 
@@ -102,7 +101,7 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
 	if (node_offset < 0) {
 		printf("WARNING: could not find compatible node %s: %s.\n",
 			compat, fdt_strerror(node_offset));
-		return;
+		return -1;
 	}
 
 	if (mode) {
@@ -121,16 +120,18 @@ static void fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
 			       prop_type, compat, fdt_strerror(err));
 	}
 
-	start_offset = node_offset;
+	return node_offset;
 }
 
 void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 {
 	const char *modes[] = { "host", "peripheral", "otg" };
-	const char *phys[] = { "ulpi", "umti" };
+	const char *phys[] = { "ulpi", "utmi" };
 	const char *mode = NULL;
 	const char *phy_type = NULL;
 	char usb1_defined = 0;
+	int usb_mode_off = -1;
+	int usb_phy_off = -1;
 	char str[5];
 	int i, j;
 
@@ -153,11 +154,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 				}
 			}
 			if (mode_idx >= 0)
-				fdt_fixup_usb_mode_phy_type(blob,
-					modes[mode_idx], NULL);
+				usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+					modes[mode_idx], NULL, usb_mode_off);
 			if (phy_idx >= 0)
-				fdt_fixup_usb_mode_phy_type(blob,
-					NULL, phys[phy_idx]);
+				usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+					NULL, phys[phy_idx], usb_phy_off);
 			if (!strcmp(str, "usb1"))
 				usb1_defined = 1;
 			if (mode_idx < 0 && phy_idx < 0)
@@ -165,11 +166,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 		}
 	}
 	if (!usb1_defined) {
+		int usb_off = -1;
 		mode = getenv("usb_dr_mode");
 		phy_type = getenv("usb_phy_type");
 		if (!mode && !phy_type)
 			return;
-		fdt_fixup_usb_mode_phy_type(blob, mode, phy_type);
+		fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
 	}
 }
 #endif /* CONFIG_HAS_FSL_DR_USB */
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index d78962ff87..587576bacf 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -107,7 +107,7 @@ void init_early_memctl_regs(void)
 void upmconfig(uint upm, uint *table, uint size)
 {
 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	int i, mdr, mad, old_mad = 0;
+	int i, mad, old_mad = 0;
 	u32 mask = (~MxMR_OP_MSK & ~MxMR_MAD_MSK);
 	u32 msel = BR_UPMx_TO_MSEL(upm);
 	u32 *mxmr = &lbc->mamr + upm;
@@ -138,7 +138,7 @@ void upmconfig(uint upm, uint *table, uint size)
 	for (i = 0; i < size; i++) {
 		out_be32(mxmr, (in_be32(mxmr) & mask) | MxMR_OP_WARR | i);
 		out_be32(&lbc->mdr, table[i]);
-		mdr = in_be32(&lbc->mdr);
+		(void)in_be32(&lbc->mdr);
 		*dummy = 0;
 		do {
 			mad = in_be32(mxmr) & MxMR_MAD_MSK;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index c3d6ba9e99..981d639796 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -64,6 +64,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index ef5076b24d..209103e3ce 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -392,17 +392,17 @@ extern void print_bats(void);
  */
 
 #define MAS0_TLBSEL_MSK	0x30000000
-#define MAS0_TLBSEL(x)	((x << 28) & MAS0_TLBSEL_MSK)
+#define MAS0_TLBSEL(x)	(((x) << 28) & MAS0_TLBSEL_MSK)
 #define MAS0_ESEL_MSK	0x0FFF0000
-#define MAS0_ESEL(x)	((x << 16) & MAS0_ESEL_MSK)
+#define MAS0_ESEL(x)	(((x) << 16) & MAS0_ESEL_MSK)
 #define MAS0_NV(x)	((x) & 0x00000FFF)
 
 #define MAS1_VALID	0x80000000
 #define MAS1_IPROT	0x40000000
-#define MAS1_TID(x)	((x << 16) & 0x3FFF0000)
+#define MAS1_TID(x)	(((x) << 16) & 0x3FFF0000)
 #define MAS1_TS		0x00001000
-#define MAS1_TSIZE(x)	((x << 8) & 0x00000F00)
-#define TSIZE_TO_BYTES(x) ((phys_addr_t)(1UL << ((tsize * 2) + 10)))
+#define MAS1_TSIZE(x)	(((x) << 8) & 0x00000F00)
+#define TSIZE_TO_BYTES(x) (1ULL << (((x) * 2) + 10))
 
 #define MAS2_EPN	0xFFFFF000
 #define MAS2_X0		0x00000040
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 1b96b84dcb..4e32639821 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -513,7 +513,13 @@
 
 #define SPRN_TLB0CFG	0x2B0	/* TLB 0 Config Register */
 #define SPRN_TLB1CFG	0x2B1	/* TLB 1 Config Register */
+#define SPRN_TLB0PS	0x158	/* TLB 0 Page Size Register */
+#define SPRN_TLB1PS	0x159	/* TLB 1 Page Size Register */
 #define SPRN_MMUCSR0	0x3f4	/* MMU control and status register 0 */
+#define SPRN_MMUCFG	0x3F7	/* MMU Configuration Register */
+#define MMUCFG_MAVN	0x00000003	/* MMU Architecture Version Number */
+#define MMUCFG_MAVN_V1	0x00000000	/* v1.0 */
+#define MMUCFG_MAVN_V2	0x00000001	/* v2.0 */
 #define SPRN_MAS0	0x270	/* MMU Assist Register 0 */
 #define SPRN_MAS1	0x271	/* MMU Assist Register 1 */
 #define SPRN_MAS2	0x272	/* MMU Assist Register 2 */