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authorLiu Gang <Gang.Liu@freescale.com>2012-08-09 05:10:00 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 10:24:14 -0500
commit81fa73bab05f491dd6f27c9afbc6952f54173b41 (patch)
tree8c10a983633f7cb3f5e3bdee8ab634094a3c36af /arch
parentff65f12699b4181b777cbc03b057510bc4605f5e (diff)
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro
When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 53d563ed0a..91228e77ea 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1758,6 +1758,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
+#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
#define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000