diff options
| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:15 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:19 -0500 |
| commit | d1001e3f0ce0059a55a870c42bac8aba2e4befec (patch) | |
| tree | bb8dd7437496f9705ab0dbd59460ed3ce60a57f4 /arch/powerpc/include/asm/fsl_serdes.h | |
| parent | fd3cebd020edad5fa18ff5a64cde3aa75aa896c8 (diff) | |
powerpc/corenet2: Add SerDes for corenet2
Create new files to handle 2nd generation Chassis as the registers are
organized differently.
- Add SerDes protocol parsing and detection
- Add support of 4 SerDes
- Add CPRI protocol in fsl_serdes.h
The Common Public Radio Interface (CPRI) is publicly available
specification that standardizes the protocol interface between the
radio equipment control (REC) and the radio equipment (RE) in wireless
basestations. This allows interoperability of equipment from different
vendors,and preserves the software investment made by wireless service
providers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/include/asm/fsl_serdes.h')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_serdes.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 22525f1156..6cd7379c8f 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -37,11 +37,17 @@ enum srds_prtcl { SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6, + SGMII_FM1_DTSEC9, + SGMII_FM1_DTSEC10, SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM2_DTSEC5, + SGMII_FM2_DTSEC6, + SGMII_FM2_DTSEC9, + SGMII_FM2_DTSEC10, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3, @@ -49,13 +55,49 @@ enum srds_prtcl { XAUI_FM1, XAUI_FM2, AURORA, + CPRI1, + CPRI2, + CPRI3, + CPRI4, + CPRI5, + CPRI6, + CPRI7, + CPRI8, + XAUI_FM1_MAC9, + XAUI_FM1_MAC10, + XAUI_FM2_MAC9, + XAUI_FM2_MAC10, + HIGIG_FM1_MAC9, + HIGIG_FM1_MAC10, + HIGIG_FM2_MAC9, + HIGIG_FM2_MAC10, + QSGMII_FM1_A, /* A indicates MACs 1-4 */ + QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */ + QSGMII_FM2_A, + QSGMII_FM2_B, + XFI_FM1_MAC9, + XFI_FM1_MAC10, + XFI_FM2_MAC9, + XFI_FM2_MAC10, + INTERLAKEN, +}; + +enum srds { + FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, + FSL_SRDS_3 = 2, + FSL_SRDS_4 = 3, }; int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); #ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 +int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +#else int serdes_get_first_lane(enum srds_prtcl device); +#endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 void serdes_reset_rx(enum srds_prtcl device); #endif |