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authorScott Wood <scottwood@freescale.com>2012-09-20 18:34:49 -0500
committerScott Wood <scottwood@freescale.com>2012-11-26 15:41:22 -0600
commit7f0a22ff25f3b63d259e27a3702a5d10254e7165 (patch)
tree0bf7c2677ca24c6dc31d4488f4349805da1998f2 /arch/powerpc/cpu/mpc85xx/start.S
parent6ec63f411e47847484b60a8b451e528d613c9dd9 (diff)
powerpc/mpc85xx: fix TLB alignment
In the RAMBOOT/SPL case we were creating a TLB entry starting at CONFIG_SYS_MONITOR_BASE, and just hoping that the base was properly aligned for the TLB entry size. This turned out to not be the case with NAND SPL because the main U-Boot starts at an offset into the image in order to skip the SPL itself. Fix the TLB entry to always start at a proper alignment. We still assume that CONFIG_SYS_MONITOR_BASE doesn't start immediately before a large-page boundary thus requiring multiple TLB entries. Signed-off-by: Scott Wood <scottwood@frescale.com> Cc: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch/powerpc/cpu/mpc85xx/start.S')
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 7912a4b249..577d6874ba 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1046,8 +1046,8 @@ create_init_ram_area:
*/
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#else
/*
@@ -1056,8 +1056,8 @@ create_init_ram_area:
*/
create_tlb1_entry 15, \
1, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
#endif