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authorBecky Bruce <beckyb@kernel.crashing.org>2010-06-17 11:37:20 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-16 10:55:09 -0500
commitf51cdaf19141151ce2b40d562a468605340f2315 (patch)
tree60b51af79796f061d119f2839d101f9584964dfc /arch/powerpc/cpu/mpc83xx/cpu_init.c
parent0914f4832887341ee073d2d2bfbada69a6872548 (diff)
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/cpu/mpc83xx/cpu_init.c')
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c53
1 files changed, 7 insertions, 46 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index f3b67ae2b9..83cba93605 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -236,8 +236,8 @@ void cpu_init_f (volatile immap_t * im)
/* LCRR - Clock Ratio Register (10.3.1.16)
* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
*/
- clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
- __raw_readl(&im->lbus.lcrr);
+ clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
+ __raw_readl(&im->im_lbc.lcrr);
isync();
/* Enable Time Base & Decrementer ( so we will have udelay() )*/
@@ -267,80 +267,41 @@ void cpu_init_f (volatile immap_t * im)
/* Config QE ioports */
config_qe_ioports();
#endif
+ /* Set up preliminary BR/OR regs */
+ init_early_memctl_regs();
- /*
- * Memory Controller:
- */
-
- /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
- * addresses - these have to be modified later when FLASH size
- * has been determined
- */
-
-#if defined(CONFIG_SYS_BR0_PRELIM) \
- && defined(CONFIG_SYS_OR0_PRELIM) \
- && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
- && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
- im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
- im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
+ /* Local Access window setup */
+#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
#else
-#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
+#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
#endif
-#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
- im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
- im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
- im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
- im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
- im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
- im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
- im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
- im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
- im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
- im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
- im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
#endif
-#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
- im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
- im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
-#endif
#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;