summaryrefslogtreecommitdiff
path: root/arch/m68k/cpu/mcf523x/interrupts.c
diff options
context:
space:
mode:
authorAlison Wang <b18965@freescale.com>2012-03-26 21:49:06 +0000
committerjason <jason@jason-ThinkPad-T61.(none)>2012-09-20 20:39:27 +0800
commitc6d88630158af79f5700c8bbc37972f511e84500 (patch)
tree4e36b504a79945811e15fa46e0c1cc48b8ede41b /arch/m68k/cpu/mcf523x/interrupts.c
parentaa0d99fc285a0b4ca71245c0c3ba8c00f8b51983 (diff)
ColdFire: Clean up checkpatch warnings for MCF523x
Signed-off-by: Alison Wang <b18965@freescale.com>
Diffstat (limited to 'arch/m68k/cpu/mcf523x/interrupts.c')
-rw-r--r--arch/m68k/cpu/mcf523x/interrupts.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/m68k/cpu/mcf523x/interrupts.c b/arch/m68k/cpu/mcf523x/interrupts.c
index db5ccdf6d3..76115a4013 100644
--- a/arch/m68k/cpu/mcf523x/interrupts.c
+++ b/arch/m68k/cpu/mcf523x/interrupts.c
@@ -1,6 +1,6 @@
/*
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -25,13 +25,14 @@
/* CPU specific interrupt routine */
#include <common.h>
#include <asm/immap.h>
+#include <asm/io.h>
int interrupt_init(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
/* Make sure all interrupts are disabled */
- intp->imrl0 |= 0x1;
+ setbits_be32(&intp->imrl0, 0x1);
enable_interrupts();
return 0;
@@ -40,10 +41,10 @@ int interrupt_init(void)
#if defined(CONFIG_MCFTMR)
void dtimer_intr_setup(void)
{
- volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
+ int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
- intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
- intp->imrl0 &= ~INTC_IPRL_INT0;
- intp->imrl0 &= ~CONFIG_SYS_TMRINTR_MASK;
+ out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
+ clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
+ clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
}
#endif