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authorStefan Roese <sr@denx.de>2015-09-02 11:10:58 +0200
committerTom Rini <trini@konsulko.com>2015-09-11 17:15:14 -0400
commitda53ba0219c65c11a673ec11c0c2ad371c74251f (patch)
treebca5a97096f86a1777519e0c592f924b49c344f6 /arch/arm/include
parent1a103c6caa0b27fcd3798267b980444f5459860f (diff)
arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4
This patch adds the "nandecc" command to switch between the SPEAr600 internal 1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND chips with a stronger ECC than 1-bit, as on the x600. And to dynamically switch between both ECC schemes for backwards compatibility. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/arch-spear/spr_misc.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index b55026ecdf..6f2e19ed61 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -253,5 +253,6 @@ struct misc_regs {
#define SOC_SPEAR320 203
extern int get_socrev(void);
+int fsmc_nand_switch_ecc(uint32_t eccstrength);
#endif