diff options
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2016-04-06 18:04:57 +0200 |
|---|---|---|
| committer | Klaus Goger <klaus.goger@theobroma-systems.com> | 2016-09-18 13:45:14 +0200 |
| commit | 5da39118172811a2fe32a4eeaee7193f8cb413ed (patch) | |
| tree | 5f942d4c7778b3de6f1e03da1338ac6811ff0010 /arch/arm/include/asm/arch-sunxi/clock_sun9i.h | |
| parent | 6ed4d8a8686a0e8da9806a42dc90f1f0b7a0c160 (diff) | |
sunxi: Support GbE controller (GMAC) for sun9i (A80)
* board/sunxi/gmac.c(eth_init_board): Add support for configuring
sun9i (A80) for Ethernet support in RGMII mode.
* arch/arm/include/asm/arch-sunxi/gpio.h (SUN9I_GPA_GMAC): Define.
* arch/arm/include/asm/arch-sunxi/clock_sun9i.h: Add Ethernet support
for sun9i (A80), defining struct sunxi_sysctl_reg (which contains
the GMAC clock control on sun9i) and AHB_{GATE,RESET}_OFFSET_GMAC
* arch/arm/include/asm/arch-sunxi/cpu_sun9i.h(SUNXI_SYSCTL_BASE):
Define.
* arch/arm/dts/sun9i-a80.dtsi: add device-tree support for GMAC on
sun9i (A80).
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi/clock_sun9i.h')
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h index 810313c5c3..1e73d7dd6a 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h @@ -96,6 +96,15 @@ struct sunxi_ccm_reg { u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ }; +struct sunxi_sysctl_reg { + u8 reserved1[0x24]; /* 0x00 */ + u32 version; /* 0x24 system version (and boot select) */ + u8 reserved2[0x8]; /* 0x28 */ + u32 gmac_clk_cfg; /* 0x30 GMAC clock control */ + u8 reserved3[0x4]; /* 0x34 */ + u32 disp_mux_cfg; /* 0x38 display MUX control */ +}; + /* pll4_periph0_cfg */ #define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */ @@ -116,6 +125,7 @@ struct sunxi_ccm_reg { #define CCM_MMC_CTRL_ENABLE (1 << 31) /* ahb_gate0 fields */ +#define AHB_GATE_OFFSET_GMAC 17 #define AHB_GATE_OFFSET_MCTL 14 /* On sun9i all sdc-s share their ahb gate, so ignore (x) */ @@ -132,6 +142,7 @@ struct sunxi_ccm_reg { #define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) /* ahb_reset0_cfg fields */ +#define AHB_RESET_OFFSET_GMAC 17 #define AHB_RESET_OFFSET_MCTL 14 /* On sun9i all sdc-s share their ahb reset, so ignore (x) */ @@ -143,6 +154,15 @@ struct sunxi_ccm_reg { #define APB1_RESET_TWI_SHIFT 0 #define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) +/* gmac_clk_cfg (in SYSCTL) fields ... these need to be misnamed as CCM_GMAC_CTRL + so we can reuse the same code as for sun6i in board/sunxi/gmac.c */ +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) +#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) +#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) #ifndef __ASSEMBLY__ unsigned int clock_get_pll4_periph0(void); |