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authorMingkai Hu <Mingkai.hu@freescale.com>2015-12-07 16:58:54 +0800
committerYork Sun <yorksun@freescale.com>2015-12-17 08:52:18 +0800
commit0d6faf2bd0d12642e8b2c428d62c285f4ee28b9d (patch)
treefbc4357334745cbdccb55e406e147f8d8789cec8 /arch/arm/cpu
parent2949ae521200ae5758ae395a364fcb4e85f899c0 (diff)
armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 984eaf903e..23d6b73e3d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -197,6 +197,19 @@ int sata_init(void)
}
#endif
+static void erratum_a009929(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
+ struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
+ u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
+
+ rstrqmr1 |= 0x00000400;
+ gur_out32(&gur->rstrqmr1, rstrqmr1);
+ writel(0x01000000, dcsr_cop_ccp);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -216,6 +229,9 @@ void fsl_lsch2_early_init_f(void)
*/
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /* Erratum */
+ erratum_a009929();
}
#endif