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authorGeert Uytterhoeven <geert+renesas@glider.be>2016-06-28 16:10:33 +0200
committerSimon Horman <horms+renesas@verge.net.au>2016-06-29 14:37:08 +0200
commit053239987f89f9a6299e78610bad010764bccd71 (patch)
tree1d65036273814dfa8e21727b4d6ddfa84b1952f0 /drivers/soc
parentb1e52287a29cf0673e1a60210d55edccc756e44a (diff)
soc: renesas: rcar-sysc: Move SYSC interrupt config to rcar-sysc driver
On R-Car H1 and Gen2, the SYSC interrupt registers are always configured using hardcoded values in platform code. For R-Car Gen2, values are provided for H2 and M2-W only, other SoCs are not yet supported, and never will be. Move this configuration from SoC-specific platform code to the rcar_sysc_init() wrapper, so it can be skipped if the SYSC is configured from DT. This would be the case not only for H1, H2, and M2-W using a modern DTS, but also for other R-Car Gen2 SoCs not supported by the platform code, relying purely on DT. There is no longer a need to return the mapped register block, hence make the function return void. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/soc')
-rw-r--r--drivers/soc/renesas/rcar-sysc.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 68d6856c9d3c..22f0d646225c 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -400,10 +400,14 @@ out_put:
}
early_initcall(rcar_sysc_pd_init);
-void __iomem * __init rcar_sysc_init(phys_addr_t base)
+void __init rcar_sysc_init(phys_addr_t base, u32 syscier)
{
- if (rcar_sysc_pd_init())
- rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
+ if (!rcar_sysc_pd_init())
+ return;
- return rcar_sysc_base;
+ rcar_sysc_base = ioremap_nocache(base, PAGE_SIZE);
+
+ /* enable all interrupt sources, but do not use interrupt handler */
+ iowrite32(syscier, rcar_sysc_base + SYSCIER);
+ iowrite32(0, rcar_sysc_base + SYSCIMR);
}