diff options
| author | Stephen Warren <swarren@nvidia.com> | 2016-07-25 16:02:21 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2016-07-26 14:57:04 -0500 |
| commit | cf5d31801278be39bd2cc28a8cf582398e58402a (patch) | |
| tree | 7457f514e90545e8aba266f44561202769ef555c /drivers/pci | |
| parent | 08203f1fac4d2c3cfab43fd157c76127f48bc5b3 (diff) | |
PCI: tegra: Program PADS_REFCLK_CFG* always, not just on legacy SoCs
tegra_pcie_phy_power_on() calls tegra_pcie_phy_enable() only for legacy
SoCs. However, part of tegra_pcie_phy_enable() needs to happen in all
cases. Move that code up one level into tegra_pcie_phy_power_on().
[bhelgaas: changelog]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pci-tegra.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index bbf77a49517d..8cac1a07077b 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -838,12 +838,6 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) value |= PADS_PLL_CTL_RST_B4SM; pads_writel(pcie, value, soc->pads_pll_ctl); - /* Configure the reference clock driver */ - value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); - pads_writel(pcie, value, PADS_REFCLK_CFG0); - if (soc->num_ports > 2) - pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); - /* wait for the PLL to lock */ err = tegra_pcie_pll_wait(pcie, 500); if (err < 0) { @@ -927,7 +921,9 @@ static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port) static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) { + const struct tegra_pcie_soc_data *soc = pcie->soc_data; struct tegra_pcie_port *port; + u32 value; int err; if (pcie->legacy_phy) { @@ -952,6 +948,13 @@ static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie) } } + /* Configure the reference clock driver */ + value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16); + pads_writel(pcie, value, PADS_REFCLK_CFG0); + + if (soc->num_ports > 2) + pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1); + return 0; } |