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authorXing Zheng <zhengxing@rock-chips.com>2016-08-24 11:29:39 -0700
committerHeiko Stuebner <heiko@sntech.de>2016-08-24 23:44:49 +0200
commita45f9d41c9dd2c28e38b9b88f69c39bc63807de9 (patch)
treea588176a7558affcff0eb958ce1c9725fc3fb461 /drivers/clk
parent4608d96fb491125657fd8183a35921e4d4e27bc8 (diff)
clk: rockchip: mark aclk_emmc_noc as a critical clock on rk3399
We don't have code to handle any of the noc clocks in rk3399 and they're all just listed as critical clocks. Let's do the same for aclk_emmc_noc. Without this clock being marked as critical we have problems around suspend/resume after commit 20c389e656a8 ("clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399"). Before that change we were presumably not actually gating any of these clocks because we were setting the wrong gate. Fixes: 20c389e656a8 ("clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399") Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/rockchip/clk-rk3399.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index ec5b2fd77c50..cdfabeb9a034 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1484,6 +1484,7 @@ static const char *const rk3399_cru_critical_clocks[] __initconst = {
"hclk_perilp1",
"hclk_perilp1_noc",
"aclk_dmac0_perilp",
+ "aclk_emmc_noc",
"gpll_hclk_perilp1_src",
"gpll_aclk_perilp0_src",
"gpll_aclk_perihp_src",