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authorRoman Volkov <rvolkov@v1ros.org>2016-01-01 16:38:12 +0300
committerArnd Bergmann <arnd@arndb.de>2016-01-07 16:04:32 +0100
commit03b9ee45bcebd1ea2811e7c90d13b6b69b0cce9b (patch)
tree2f20e7d867800e8102c5765e393275ce721cb986 /arch/arm/boot/dts/wm8505.dtsi
parent9962b3d4f0788e8637211d7b999dcea60430df18 (diff)
dts: vt8500: Fix errors in SDHC node for WM8505
According to datasheet, the registers space of SDHC controller is 1Kb, not '0x1000', the correct value should be '0x400'. Bracket interrupt numbers individually per recommendations. Signed-off-by: Roman Volkov <rvolkov@v1ros.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/wm8505.dtsi')
-rw-r--r--arch/arm/boot/dts/wm8505.dtsi4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/wm8505.dtsi b/arch/arm/boot/dts/wm8505.dtsi
index a1a854b8a454..e9ef539e13d3 100644
--- a/arch/arm/boot/dts/wm8505.dtsi
+++ b/arch/arm/boot/dts/wm8505.dtsi
@@ -281,8 +281,8 @@
sdhc@d800a000 {
compatible = "wm,wm8505-sdhc";
- reg = <0xd800a000 0x1000>;
- interrupts = <20 21>;
+ reg = <0xd800a000 0x400>;
+ interrupts = <20>, <21>;
clocks = <&clksdhc>;
bus-width = <4>;
};