clk: sunxi: Add cpu clock support for the sun9i (A80)

The calculation of the PLL factors (N and P) for PLL_C0CPUX and
PLL_C1CPUX on the sun9iw1p1 (Allwinner A80) does not fully model
the encoding of the factor P (external divider).  Consequently,
we force the frequency of these clocks to be above 288MHz.

The AXI0 and AXI1 clocks are derived from the C0CPUX and C1CPUX
mux-outputs using a divider.  Qualification of the A80-Q7 module
shows that 600MHz is a reasonable limit for both AXI clocks
providing good performance while mainaining system reliability.
The original Linux 3.4 BSP from Allwinner set these dividers
through the CPUS firmware (the settings used are listed in their
cpufreq driver) cpufreq support.

Our earlier bootloader versions for the A80-Q7 set the dividers
to their worst-case settings and kept these unchanged through the
system runtime.  However, when performing DVFS, this would reduce
system performance.  We now use a notifier to perform adjustments
before and after rate changes to keep the the AXI operating as
close to, but below, 600MHz.

Full support for the AXI divider uses the following device-tree
bindings:

- the AXI divider registers need to be modeled as "syscon"
  devices, as in this example:

  axi1: c1cpux_clkcfg@06000058 {
    compatible = "allwinner,sun9i-a80-c1clkcfg", "syscon";
    reg = <0x06000058 0x4>;
  };

- the CPU-clock needs to refer to these entries (and should
  provide a sane default for the AXI divider to be used during
  bootup):

    allwinner,sun9i-a80-clkcfg = <&axi1>;
    allwinner,sun9i-a80-clkcfg-default = <0x102>;

If any of these are missing, some of the functionality (or even
all) to keep the AXI clocks within their limits will be disabled.
If the bootloader sets us up with a conservative setting, this
will still be okay.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

0 files changed, 0 insertions, 0 deletions