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authorChen-Yu Tsai <wens@csie.org>2016-01-21 13:26:42 +0800
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-01-25 00:01:21 +0100
commit8826532c76da7e6f157aa319dbf358c067f5877f (patch)
treef67906b9ebc0ac733e131d3d1677b0bae06e2935 /arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
parent02df9cb85e156924339f2244aec29dcc37d9ab8c (diff)
ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC
mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun9i-a80-cubieboard4.dts')
-rw-r--r--arch/arm/boot/dts/sun9i-a80-cubieboard4.dts6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index 382bd9fc5647..eb2ccd0a3bd5 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -111,9 +111,15 @@
vmmc-supply = <&reg_vcc3v0>;
bus-width = <8>;
non-removable;
+ cap-mmc-hw-reset;
status = "okay";
};
+&mmc2_8bit_pins {
+ /* Increase drive strength for DDR modes */
+ allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
&r_ir {
status = "okay";
};