diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2015-11-23 14:55:59 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2015-11-25 10:42:19 +0900 |
| commit | 374e70075e58acfe922869aad1202b29f8fb76f5 (patch) | |
| tree | f0e465742b211a83e6a4c3eb96f58524207319a3 /arch/arm/boot/dts/r8a7740.dtsi | |
| parent | c175e7abf75f174a781d1218aa6fb2bdf2ff3eae (diff) | |
ARM: shmobile: r8a7740 dtsi: Add L2 cache-controller node
Add the missing L2 cache-controller node, and link the CPU node to it.
This will allow migration to the generic l2c OF initialization.
The L2 cache is an ARM L2C-310 (r3p1-150rel0), of size 256 KiB (32 KiB x
8 ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7740.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7740.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index e14cb1438216..7676646f7085 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -26,6 +26,7 @@ reg = <0x0>; clock-frequency = <800000000>; power-domains = <&pd_a3sm>; + next-level-cache = <&L2>; }; }; @@ -37,6 +38,18 @@ <0xc2000000 0x1000>; }; + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xf0100000 0x1000>; + interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_a3sm>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,shared-override; + cache-unified; + cache-level = <2>; + }; + dbsc3: memory-controller@fe400000 { compatible = "renesas,dbsc3-r8a7740"; reg = <0xfe400000 0x400>; |