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authorRoland Stigge <stigge@antcom.de>2012-05-19 12:28:53 +0200
committerOlof Johansson <olof@lixom.net>2012-05-30 16:15:53 -0700
commita035254aefe5a6c0b45c8c55588ab47403c674ed (patch)
tree79e27ac2e50d52d178bda53fa2b4241fcd46975e /arch/arm/boot/dts/lpc32xx.dtsi
parentaf56e0aa35f3ae2a4c1a6d1000702df1dd78cb76 (diff)
ARM: LPC32xx: Adjust dts files to gpio dt binding
The GPIO devicetree binding in 3.5 doesn't register the various LPC32xx GPIO banks via DT subnodes but always all at once, and changes the gpio referencing to 3 cells (bank, gpio, flags). This patch adjusts the DTS files to this binding that was just accepted to the gpio subsystem. Signed-off-by: Roland Stigge <stigge@antcom.de> Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/lpc32xx.dtsi')
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi41
1 files changed, 2 insertions, 39 deletions
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 2d696866f71c..3f5dad801a98 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -215,45 +215,8 @@
gpio: gpio@40028000 {
compatible = "nxp,lpc3220-gpio";
reg = <0x40028000 0x1000>;
- /* create a private address space for enumeration */
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio_p0: gpio-bank@0 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0>;
- };
-
- gpio_p1: gpio-bank@1 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <1>;
- };
-
- gpio_p2: gpio-bank@2 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <2>;
- };
-
- gpio_p3: gpio-bank@3 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <3>;
- };
-
- gpi_p3: gpio-bank@4 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <4>;
- };
-
- gpo_p3: gpio-bank@5 {
- gpio-controller;
- #gpio-cells = <2>;
- reg = <5>;
- };
+ gpio-controller;
+ #gpio-cells = <3>; /* bank, pin, flags */
};
watchdog@4003C000 {