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aarch64
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cpu_helpers.S
Age
Commit message (
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Author
2017-05-24
Use a callee-saved register to be AAPCS-compliant
dp-arm
2017-05-03
Use SPDX license identifiers
dp-arm
2017-04-20
Remove build option `ASM_ASSERTION`
Antonio Nino Diaz
2017-03-20
Add workaround for ARM Cortex-A53 erratum 855873
Andre Przywara
2017-01-30
Report errata workaround status to console
Jeenu Viswambharan
2017-01-24
Use #ifdef for IMAGE_BL* instead of #if
Masahiro Yamada
2017-01-17
Correct system include order
David Cunado
2016-12-15
Add provision to extend CPU operations at more levels
Jeenu Viswambharan
2016-03-22
Make cpu operations warning a VERBOSE print
Soby Mathew
2016-02-08
Disable non-temporal hint on Cortex-A53/57
Sandrine Bailleux
2015-04-08
Add support to indicate size and end of assembly functions
Kévin Petit
2015-03-13
Initialise cpu ops after enabling data cache
Vikram Kanigiri
2015-01-30
Fix the Cortex-A57 reset handler register usage
Soby Mathew
2015-01-26
Call reset handlers upon BL3-1 entry.
Yatharth Kochar
2015-01-13
Invalidate the dcache after initializing cpu-ops
Soby Mathew
2014-10-29
Apply errata workarounds only when major/minor revisions match.
Soby Mathew
2014-08-20
Add CPU specific crash reporting handlers
Soby Mathew
2014-08-20
Add CPU specific power management operations
Soby Mathew
2014-08-20
Add platform API for reset handling
Soby Mathew
2014-08-20
Introduce framework for CPU specific operations
Soby Mathew