diff options
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-02-21 14:40:44 +0000 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-05-02 16:11:12 +0100 |
| commit | f4c8aa905414fb021c08370306bd516f678a58bd (patch) | |
| tree | 7f727d80afb45c86cf12203e66d49bf23d5bd0b6 /plat | |
| parent | 7fa3214e18ad640208eaf6c8d6111ec53f3894aa (diff) | |
Add macro to check whether the CPU implements an EL
Replace all instances of checks with the new macro.
Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/arm/common/arm_common.c | 6 | ||||
| -rw-r--r-- | plat/mediatek/mt6795/bl31_plat_setup.c | 9 | ||||
| -rw-r--r-- | plat/qemu/qemu_bl2_setup.c | 6 |
3 files changed, 4 insertions, 17 deletions
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c index 3d67ef76..ffd7b7ee 100644 --- a/plat/arm/common/arm_common.c +++ b/plat/arm/common/arm_common.c @@ -137,15 +137,11 @@ uint32_t arm_get_spsr_for_bl32_entry(void) #ifndef AARCH32 uint32_t arm_get_spsr_for_bl33_entry(void) { - unsigned long el_status; unsigned int mode; uint32_t spsr; /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; + mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; /* * TODO: Consider the possibility of specifying the SPSR in diff --git a/plat/mediatek/mt6795/bl31_plat_setup.c b/plat/mediatek/mt6795/bl31_plat_setup.c index af0858f0..1ba8b145 100644 --- a/plat/mediatek/mt6795/bl31_plat_setup.c +++ b/plat/mediatek/mt6795/bl31_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -360,20 +360,15 @@ void enable_ns_access_to_cpuectlr(void) static entry_point_info_t *bl31_plat_get_next_kernel64_ep_info(void) { entry_point_info_t *next_image_info; - unsigned long el_status; unsigned int mode; - el_status = 0; mode = 0; /* Kernel image is always non-secured */ next_image_info = &bl33_image_ep_info; /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - if (el_status) { + if (EL_IMPLEMENTED(2)) { INFO("Kernel_EL2\n"); mode = MODE_EL2; } else{ diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c index 738d671a..6c599744 100644 --- a/plat/qemu/qemu_bl2_setup.c +++ b/plat/qemu/qemu_bl2_setup.c @@ -226,15 +226,11 @@ static uint32_t qemu_get_spsr_for_bl32_entry(void) ******************************************************************************/ static uint32_t qemu_get_spsr_for_bl33_entry(void) { - unsigned long el_status; unsigned int mode; uint32_t spsr; /* Figure out what mode we enter the non-secure world in */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; + mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; /* * TODO: Consider the possibility of specifying the SPSR in |