diff options
| author | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-11-14 12:01:04 +0000 |
|---|---|---|
| committer | dp-arm <dimitris.papastamos@arm.com> | 2017-04-20 15:05:21 +0100 |
| commit | 07570d592ea5b8a0ea22f23d2d502782b9d6c1c5 (patch) | |
| tree | 7744838900739daf5cb61d5623c298abd7c403b3 /include | |
| parent | dc787588a557d09fbf46c8562d7060cd39e275d9 (diff) | |
Changes to support execution in AArch32 state for JUNO
Following steps are required to boot JUNO in AArch32 state:
1> BL1, in AArch64 state, loads BL2.
2> BL2, in AArch64 state, initializes DDR.
Loads SP_MIN & BL33 (AArch32 executable)images.
Calls RUN_IMAGE SMC to go back to BL1.
3> BL1 writes AArch32 executable opcodes, to load and branch
at the entrypoint address of SP_MIN, at HI-VECTOR address and
then request for warm reset in AArch32 state using RMR_EL3.
This patch makes following changes to facilitate above steps:
* Added assembly function to carry out step 3 above.
* Added region in TZC that enables Secure access to the
HI-VECTOR(0xFFFF0000) address space.
* AArch32 image descriptor is used, in BL2, to load
SP_MIN and BL33 AArch32 executable images.
A new flag `JUNO_AARCH32_EL3_RUNTIME` is introduced that
controls above changes. By default this flag is disabled.
NOTE: BL1 and BL2 are not supported in AArch32 state for JUNO.
Change-Id: I091d56a0e6d36663e6d9d2bb53c92c672195d1ec
Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com>
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/aarch64/arch.h | 10 | ||||
| -rw-r--r-- | include/plat/arm/common/plat_arm.h | 1 | ||||
| -rw-r--r-- | include/plat/arm/soc/common/soc_css_def.h | 11 |
3 files changed, 20 insertions, 2 deletions
diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h index d766490d..4b323d33 100644 --- a/include/lib/aarch64/arch.h +++ b/include/lib/aarch64/arch.h @@ -261,6 +261,16 @@ #define DISABLE_ALL_EXCEPTIONS \ (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) +/* + * RMR_EL3 definitions + */ +#define RMR_EL3_RR_BIT (1 << 1) +#define RMR_EL3_AA64_BIT (1 << 0) + +/* + * HI-VECTOR address for AArch32 state + */ +#define HI_VECTOR_BASE (0xFFFF0000) /* * TCR defintions diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index b24af78d..d68a3e3b 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -157,6 +157,7 @@ void arm_bl2_platform_setup(void); void arm_bl2_plat_arch_setup(void); uint32_t arm_get_spsr_for_bl32_entry(void); uint32_t arm_get_spsr_for_bl33_entry(void); +int arm_bl2_handle_post_image_load(unsigned int image_id); /* BL2U utility functions */ void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, diff --git a/include/plat/arm/soc/common/soc_css_def.h b/include/plat/arm/soc/common/soc_css_def.h index 3b4cc79f..efd78f04 100644 --- a/include/plat/arm/soc/common/soc_css_def.h +++ b/include/plat/arm/soc/common/soc_css_def.h @@ -96,9 +96,16 @@ /* * Required platform porting definitions common to all ARM CSS SoCs */ - +#if JUNO_AARCH32_EL3_RUNTIME +/* + * Following change is required to initialize TZC + * for enabling access to the HI_VECTOR (0xFFFF0000) + * location needed for JUNO AARCH32 support. + */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000) +#else /* 2MB used for SCP DDR retraining */ #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) - +#endif #endif /* __SOC_CSS_DEF_H__ */ |