diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2017-04-21 17:10:27 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2017-04-21 17:10:27 +0100 |
| commit | 484acce376e63b228befb06f3d10d0caf7067091 (patch) | |
| tree | 5c8a4105ae878e70d19211ed99a6a53a0394ce5d /include/plat | |
| parent | 94e0ed6052352c1f0b90d43253f78fc98b1b7f12 (diff) | |
| parent | 6f249345e2aa2343ce67222e82dafc539e973ec5 (diff) | |
Merge pull request #910 from dp-arm/dp/AArch32-juno-port
Add AArch32 support for Juno
Diffstat (limited to 'include/plat')
| -rw-r--r-- | include/plat/arm/common/plat_arm.h | 3 | ||||
| -rw-r--r-- | include/plat/arm/soc/common/soc_css_def.h | 11 |
2 files changed, 11 insertions, 3 deletions
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index 5a2a9215..4ba4a845 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -81,7 +81,7 @@ void arm_setup_page_tables(uintptr_t total_base, #else /* - * Empty macros for all other BL stages other than BL31 + * Empty macros for all other BL stages other than BL31 and BL32 */ #define ARM_INSTANTIATE_LOCK #define arm_lock_init() @@ -157,6 +157,7 @@ void arm_bl2_platform_setup(void); void arm_bl2_plat_arch_setup(void); uint32_t arm_get_spsr_for_bl32_entry(void); uint32_t arm_get_spsr_for_bl33_entry(void); +int arm_bl2_handle_post_image_load(unsigned int image_id); /* BL2U utility functions */ void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, diff --git a/include/plat/arm/soc/common/soc_css_def.h b/include/plat/arm/soc/common/soc_css_def.h index 3b4cc79f..efd78f04 100644 --- a/include/plat/arm/soc/common/soc_css_def.h +++ b/include/plat/arm/soc/common/soc_css_def.h @@ -96,9 +96,16 @@ /* * Required platform porting definitions common to all ARM CSS SoCs */ - +#if JUNO_AARCH32_EL3_RUNTIME +/* + * Following change is required to initialize TZC + * for enabling access to the HI_VECTOR (0xFFFF0000) + * location needed for JUNO AARCH32 support. + */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x8000) +#else /* 2MB used for SCP DDR retraining */ #define PLAT_ARM_SCP_TZC_DRAM1_SIZE ULL(0x00200000) - +#endif #endif /* __SOC_CSS_DEF_H__ */ |