diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2015-11-25 17:00:44 +0000 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2015-12-09 11:34:10 +0000 |
| commit | 85d80e557803a8f3e966a0b58dc036aa8c33f153 (patch) | |
| tree | 52ccd1adfc3362a4259bfe07da725d6a0a135587 /bl31 | |
| parent | 05a91fb008c31f939a9590318e2914b44cdad165 (diff) | |
Initialize VTTBR_EL2 when bypassing EL2
In the situation that EL1 is selected as the exception level for the
next image upon BL31 exit for a processor that supports EL2, the
context management code must configure all essential EL2 register
state to ensure correct execution of EL1.
VTTBR_EL2 should be part of this set of EL2 registers because:
- The ARMv8-A architecture does not define a reset value for this
register.
- Cache maintenance operations depend on VTTBR_EL2.VMID even when
non-secure EL1&0 stage 2 address translation are disabled.
This patch initializes the VTTBR_EL2 register to 0 when bypassing EL2
to address this issue. Note that this bug has not yet manifested
itself on FVP or Juno because VTTBR_EL2.VMID resets to 0 on the
Cortex-A53 and Cortex-A57.
Change-Id: I58ce2d16a71687126f437577a506d93cb5eecf33
Diffstat (limited to 'bl31')
| -rw-r--r-- | bl31/context_mgmt.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c index 6d405343..2b619aaa 100644 --- a/bl31/context_mgmt.c +++ b/bl31/context_mgmt.c @@ -330,6 +330,14 @@ void cm_prepare_el3_exit(uint32_t security_state) /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ write_vpidr_el2(read_midr_el1()); write_vmpidr_el2(read_mpidr_el1()); + + /* + * Reset VTTBR_EL2. + * Needed because cache maintenance operations depend on + * the VMID even when non-secure EL1&0 stage 2 address + * translation are disabled. + */ + write_vttbr_el2(0); } } |