diff options
| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-02-21 14:40:44 +0000 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2017-05-02 16:11:12 +0100 |
| commit | f4c8aa905414fb021c08370306bd516f678a58bd (patch) | |
| tree | 7f727d80afb45c86cf12203e66d49bf23d5bd0b6 /bl1 | |
| parent | 7fa3214e18ad640208eaf6c8d6111ec53f3894aa (diff) | |
Add macro to check whether the CPU implements an EL
Replace all instances of checks with the new macro.
Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_context_mgmt.c | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/bl1/aarch64/bl1_context_mgmt.c b/bl1/aarch64/bl1_context_mgmt.c index 972c7f68..d226f61a 100644 --- a/bl1/aarch64/bl1_context_mgmt.c +++ b/bl1/aarch64/bl1_context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -72,8 +72,7 @@ void bl1_prepare_next_image(unsigned int image_id) * Ensure that the build flag to save AArch32 system registers in CPU * context is not set for AArch64-only platforms. */ - if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT) - & ID_AA64PFR0_ELX_MASK) == 0x1) { + if (EL_IMPLEMENTED(1) == EL_IMPL_A64ONLY) { ERROR("EL1 supports AArch64-only. Please set build flag " "CTX_INCLUDE_AARCH32_REGS = 0"); panic(); @@ -99,9 +98,8 @@ void bl1_prepare_next_image(unsigned int image_id) next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } else { - /* Use EL2 if supported else use EL1. */ - if (read_id_aa64pfr0_el1() & - (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { + /* Use EL2 if supported; else use EL1. */ + if (EL_IMPLEMENTED(2)) { next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } else { |