diff options
| author | Gerald Lejeune <gerald.lejeune@st.com> | 2016-03-22 09:29:23 +0100 |
|---|---|---|
| committer | Gerald Lejeune <gerald.lejeune@st.com> | 2016-03-30 17:26:23 +0200 |
| commit | adb4fcfb4c515a9b9af68d386ed1350505480655 (patch) | |
| tree | 9087d2aa75bc34f41290504025576434a1947786 /bl1 | |
| parent | 6b1ca8f35802fddc530e1a5f2be7b82ddbab6917 (diff) | |
Enable asynchronous abort exceptions during boot
Asynchronous abort exceptions generated by the platform during cold boot are
not taken in EL3 unless SCR_EL3.EA is set.
Therefore EA bit is set along with RES1 bits in early BL1 and BL31 architecture
initialisation. Further write accesses to SCR_EL3 preserve these bits during
cold boot.
A build flag controls SCR_EL3.EA value to keep asynchronous abort exceptions
being trapped by EL3 after cold boot or not.
For further reference SError Interrupts are also known as asynchronous external
aborts.
On Cortex-A53 revisions below r0p2, asynchronous abort exceptions are taken in
EL3 whatever the SCR_EL3.EA value is.
Fixes arm-software/tf-issues#368
Signed-off-by: Gerald Lejeune <gerald.lejeune@st.com>
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_arch_setup.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c index 6a3f0623..61c01e19 100644 --- a/bl1/aarch64/bl1_arch_setup.c +++ b/bl1/aarch64/bl1_arch_setup.c @@ -38,7 +38,7 @@ void bl1_arch_setup(void) { /* Set the next EL to be AArch64 */ - write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT); + write_scr_el3(read_scr_el3() | SCR_RW_BIT); } /******************************************************************************* |