index
:
ampere-computing/llvm.git
release_60-f1b37feef3d-amp-20180630
release_70-e8af9b4c407-amp-20181130
LLVM including Ampere Computing toolchain specific patches
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
utils
/
TableGen
/
RegisterBankEmitter.cpp
Age
Commit message (
Expand
)
Author
2018-05-14
Rename DEBUG macro to LLVM_DEBUG.
Nicola Zaghen
2017-11-01
[globalisel][regbank] Warn about MIR ambiguities when register bank/class nam...
Daniel Sanders
2017-10-11
Revert "[ADT] Make Twine's copy constructor private."
Zachary Turner
2017-10-11
[ADT] Make Twine's copy constructor private.
Zachary Turner
2017-09-14
TableGen support for parameterized register class information
Krzysztof Parzyszek
2017-07-07
[TableGen] Fix some mismatches in the use of Namespace fields versus Target n...
Craig Topper
2017-05-31
[TableGen] Adapt more places to getValueAsString now returning a StringRef in...
Craig Topper
2017-01-30
TableGen: Fix infinite recursion in RegisterBankEmitter
Tom Stellard
2017-01-20
[globalisel] Fix an unused variable warning when NDEBUG is defined.
Daniel Sanders
2017-01-19
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Daniel Sanders
2017-01-18
Re-revert: [globalisel] Tablegen-erate current Register Bank Information
Daniel Sanders
2017-01-18
Re-commit: [globalisel] Tablegen-erate current Register Bank Information
Daniel Sanders
2017-01-16
Revert r292132: [globalisel] Tablegen-erate current Register Bank Information...
Daniel Sanders
2017-01-16
[globalisel] Tablegen-erate current Register Bank Information
Daniel Sanders