summaryrefslogtreecommitdiff
path: root/tools/llvm-mca
AgeCommit message (Expand)Author
2018-08-01[llvm-mca] Improve code comments. NFC.Andrea Di Biagio
2018-07-31[llvm-mca] Update the help text to reflect "physical" registers. NFC.Matt Davis
2018-07-31[llvm-mca] Remove README.txtAndrea Di Biagio
2018-07-31[llvm-mca][BtVer2] Teach how to identify dependency-breaking idioms.Andrea Di Biagio
2018-07-26[MCA] Avoid an InstrDesc copy in mca::LSUnit::reserve.Dean Michael Berris
2018-07-15[llvm-mca][BtVer2] teach how to identify false dependencies on partially writtenAndrea Di Biagio
2018-07-14[llvm-mca] Turn InstructionTables into a Stage.Matt Davis
2018-07-14[llvm-mca] Remove unused InstRef formal from pre and post execute callbacks. ...Matt Davis
2018-07-13[llvm-mca] Improve a few debug prints. NFCAndrea Di Biagio
2018-07-13[llvm-mca] Simplify the Pipeline constructor. NFCAndrea Di Biagio
2018-07-13[llvm-mca] Removed unused arguments from methods in class Pipeline. NFCAndrea Di Biagio
2018-07-12[llvm-mca] Constify SourceMgr::hasNext. NFC.Matt Davis
2018-07-12[llvm-mca] Add cycleBegin/cycleEnd callbacks to mca::Stage.Matt Davis
2018-07-12[llvm-mca] Simplify eventing by adding an onEvent templated method.Matt Davis
2018-07-11[llvm-mca] Use a different character to flag instructions with side-effects i...Andrea Di Biagio
2018-07-09[llvm-mca] report an error if the assembly sequence contains an unsupported i...Andrea Di Biagio
2018-07-06[llvm-mca] Add HardwareUnit and Context classes.Matt Davis
2018-07-06[llvm-mca] A write latency cannot be a negative value. NFCAndrea Di Biagio
2018-07-06[llvm-mca] improve the instruction issue logic implemented by the Scheduler.Andrea Di Biagio
2018-07-05[llvm-mca] Fix RegisterFile debug prints. NFCAndrea Di Biagio
2018-07-02[llvm-mca] Clear the content of map VariantDescriptors in InstrBuilder before...Andrea Di Biagio
2018-07-02[MC] Error on a .zerofill directive in a non-virtual sectionFrancis Visoiu Mistrih
2018-06-29[llvm-mca] Remove field HasReadAdvanceEntries from class ReadDescriptor.Andrea Di Biagio
2018-06-28[llvm-mca] Delete Pipeline's copy ctor and assignement operator.Matt Davis
2018-06-28[llvm-mca] Use a WriteRef to describe register writes in class RegisterFile.Andrea Di Biagio
2018-06-28[llvm-mca] Refactor method RegisterFile::collectWrites(). NFCIAndrea Di Biagio
2018-06-27[llvm-mca] Register listeners with stages; remove Pipeline dependency from S...Matt Davis
2018-06-27[llvm-mca] Avoid calling method update() on instructions that are already in ...Andrea Di Biagio
2018-06-27[llvm-mca] Add a comment to Stage::execute and fix a spelling error. NFC.Matt Davis
2018-06-26[llvm-mca] Removed wrong NDEBUG guards introduced by my last commit.Andrea Di Biagio
2018-06-26[llvm-mca] Remove unused header files and correctly guard some include header...Andrea Di Biagio
2018-06-25[llvm-mca] Rename Backend to Pipeline. NFC.Matt Davis
2018-06-22[llvm-mca] Remove unnecessary include and forward decl in RCU. NFC.Matt Davis
2018-06-22[llvm-mca] Remove redundant call. NFCAndrea Di Biagio
2018-06-22[llvm-mca] Set the operand ID for implicit register reads/writes. NFCAndrea Di Biagio
2018-06-22[llvm-mca] Introduce a sequential container of StagesMatt Davis
2018-06-21[llvm-mca] Updates comment in code, and remove some stale comments. NFCAndrea Di Biagio
2018-06-20[llvm-mca] use APint::operator[] to obtain the bit value. NFCAndrea Di Biagio
2018-06-20[llvm-mca][X86] Teach how to identify register writes that implicitly clear t...Andrea Di Biagio
2018-06-18[llvm-mca] Cleanup the header syntax line. Fix a comment. NFC.Matt Davis
2018-06-18[llvm-mca] Use an ordered map to collect hardware statistics. NFC.Andrea Di Biagio
2018-06-15[MCA] Add -summary-view optionRoman Lebedev
2018-06-14[llvm-mca] Clean up the header comment. NFC.Matt Davis
2018-06-14[llvm-mca] Introduce the ExecuteStage (was originally the Scheduler class).Matt Davis
2018-06-13[llvm-mca] Fixed a bug in the logic that checks if a memory operation is read...Andrea Di Biagio
2018-06-13Revert: [llvm-mca] Flush the output stream before we start the analysis of a ...Andrea Di Biagio
2018-06-13[llvm-mca] Flush the output stream before we start the analysis of a new code...Andrea Di Biagio
2018-06-05[llvm-mca] Correctly update the CyclesLeft of a register read in the presence...Andrea Di Biagio
2018-06-04[RFC][patch 3/3] Add support for variant scheduling classes in llvm-mca.Andrea Di Biagio
2018-06-04[llvm-mca] Track cycles contributed by resources that are in a 'Super' relati...Andrea Di Biagio
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 01:29:59 +0000