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path: root/test/CodeGen/Hexagon
AgeCommit message (Expand)Author
2018-01-02[Hexagon] Fix generation of vector sign extensionsKrzysztof Parzyszek
2017-12-20[Hexagon] Allow construction of HVX vector predicatesKrzysztof Parzyszek
2017-12-20[Hexagon] Adjust the value type for BCvt in LowerFormalArgumentsKrzysztof Parzyszek
2017-12-18[Hexagon] Cache loads to select to avoid traversing mutating DAGKrzysztof Parzyszek
2017-12-18[Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek
2017-12-15[Hexagon] Handle concat_vectors of all allowed HVX typesKrzysztof Parzyszek
2017-12-15[Hexagon] Fix operand-swapping PatFrag for atomic storesKrzysztof Parzyszek
2017-12-14[Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek
2017-12-12[Hexagon] Relax some checks in testcases, NFCKrzysztof Parzyszek
2017-12-12[Hexagon] Better detection of identity and undef masks in shufflesKrzysztof Parzyszek
2017-12-12[Hexagon] Fix wrong order of operands for vmuxKrzysztof Parzyszek
2017-12-12[MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry
2017-12-11[Hexagon] Add support for Hexagon V65Krzysztof Parzyszek
2017-12-11[Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek
2017-12-07[Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-06[Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specificallyKrzysztof Parzyszek
2017-12-06[Hexagon] Handle perfect shuffles on single vectorsKrzysztof Parzyszek
2017-12-06[Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-30[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mirKrzysztof Parzyszek
2017-11-30[Hexagon] Fix wrong pass in testcaseKrzysztof Parzyszek
2017-11-30[Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-29[Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek
2017-11-28[Hexagon] Make sure to zero-extend bytes before building a vectorKrzysztof Parzyszek
2017-11-22[Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek
2017-11-22[Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek
2017-11-22[Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek
2017-11-21[Hexagon] Make sure that RDF does not remove EH_LABELsKrzysztof Parzyszek
2017-11-02[Hexagon] Prefer L2_loadrub_io over L4_loadrub_rrKrzysztof Parzyszek
2017-10-27[Hexagon] Adjust patterns to reflect instruction selection preferencesKrzysztof Parzyszek
2017-10-27[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cppKrzysztof Parzyszek
2017-10-25[Hexagon] Account for negative offset when limiting max deviationKrzysztof Parzyszek
2017-10-24MIR: Print the register class or bank in vreg defsJustin Bogner
2017-10-23[Hexagon] Return the correct chain edge for i1 function callsKrzysztof Parzyszek
2017-10-23[Hexagon] Add extra pattern for S4_addaddiKrzysztof Parzyszek
2017-10-20[Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek
2017-10-20[Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek
2017-10-20[Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek
2017-10-20[Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek
2017-10-19[Hexagon] Fix store conversion from rr to io in optimize addressing modesKrzysztof Parzyszek
2017-10-18[Hexagon] New HVX target features.Sumanth Gundapaneni
2017-10-13[Hexagon] Minimize number of repeated constant extendersKrzysztof Parzyszek
2017-10-13[Hexagon] Add patterns for cmpb/cmph with immediate argumentsKrzysztof Parzyszek
2017-10-11[Hexagon] Make sure that new-value jump is packetized with producerKrzysztof Parzyszek
2017-10-11[Pipeliner] Improve serialization order for post-incrementsKrzysztof Parzyszek
2017-10-02[Hexagon] Check vector elements for equivalence in the HexagonVectorLoopCarri...Ron Lieberman
2017-10-02[Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman