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path: root/test/CodeGen/Hexagon
AgeCommit message (Expand)Author
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-30[Hexagon] Fix wrong check in test/CodeGen/Hexagon/newvaluejump-solo.mirKrzysztof Parzyszek
2017-11-30[Hexagon] Fix wrong pass in testcaseKrzysztof Parzyszek
2017-11-30[Hexagon] Solo instructions cannot be used with new value jumpsKrzysztof Parzyszek
2017-11-30[CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih
2017-11-30[CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih
2017-11-29[Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek
2017-11-28[Hexagon] Make sure to zero-extend bytes before building a vectorKrzysztof Parzyszek
2017-11-22[Hexagon] Implement buildVector32 and buildVector64 as utility functionsKrzysztof Parzyszek
2017-11-22[Hexagon] Add patterns to select A2_combine_ll and its variantsKrzysztof Parzyszek
2017-11-22[Hexagon] Remove trailing spaces, NFCKrzysztof Parzyszek
2017-11-21[Hexagon] Make sure that RDF does not remove EH_LABELsKrzysztof Parzyszek
2017-11-02[Hexagon] Prefer L2_loadrub_io over L4_loadrub_rrKrzysztof Parzyszek
2017-10-27[Hexagon] Adjust patterns to reflect instruction selection preferencesKrzysztof Parzyszek
2017-10-27[Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cppKrzysztof Parzyszek
2017-10-25[Hexagon] Account for negative offset when limiting max deviationKrzysztof Parzyszek
2017-10-24MIR: Print the register class or bank in vreg defsJustin Bogner
2017-10-23[Hexagon] Return the correct chain edge for i1 function callsKrzysztof Parzyszek
2017-10-23[Hexagon] Add extra pattern for S4_addaddiKrzysztof Parzyszek
2017-10-20[Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek
2017-10-20[Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek
2017-10-20[Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek
2017-10-20[Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek
2017-10-19[Hexagon] Fix store conversion from rr to io in optimize addressing modesKrzysztof Parzyszek
2017-10-18[Hexagon] New HVX target features.Sumanth Gundapaneni
2017-10-13[Hexagon] Minimize number of repeated constant extendersKrzysztof Parzyszek
2017-10-13[Hexagon] Add patterns for cmpb/cmph with immediate argumentsKrzysztof Parzyszek
2017-10-11[Hexagon] Make sure that new-value jump is packetized with producerKrzysztof Parzyszek
2017-10-11[Pipeliner] Improve serialization order for post-incrementsKrzysztof Parzyszek
2017-10-02[Hexagon] Check vector elements for equivalence in the HexagonVectorLoopCarri...Ron Lieberman
2017-10-02[Hexagon] Patch to Extract i1 element from vector of i1Ron Lieberman
2017-09-27Reverted r313993.Galina Kistanova
2017-09-22Check vector elements for equivalence in the HexagonVectorLoopCarriedReuse passPranav Bhandarkar
2017-09-21[Hexagon] - Fix testcase for the HexagonVectorLoopCarriedReuse pass.Pranav Bhandarkar
2017-09-21Revert "Add a testfile that I missed in a previous commit that added HexagonV...Rafael Espindola
2017-09-21Add a testfile that I missed in a previous commit thatPranav Bhandarkar
2017-09-14[IfConversion] More simple, correct dead/kill liveness handlingKrzysztof Parzyszek
2017-09-08Preserve existing regs when adding pristines to LivePhysRegs/LiveRegUnitsKrzysztof Parzyszek
2017-09-06Insert IMPLICIT_DEFS for undef uses in tail mergingMatthias Braun
2017-09-06[IfConversion] Remove kill flags from common instructions as wellKrzysztof Parzyszek
2017-09-06[Hexagon] Add option to generate calls to "abort" for "unreachable"Krzysztof Parzyszek
2017-08-28[Hexagon] Check for potential bank conflicts in post-RA schedulingKrzysztof Parzyszek
2017-08-24[Hexagon] Generate correct runtime check when recognizing memmoveKrzysztof Parzyszek
2017-08-09[Hexagon] Ignore DBG_VALUEs when counting instructions in hexagon-early-ifKrzysztof Parzyszek
2017-08-09[LSR / TTI / SystemZ] Eliminate TargetTransformInfo::isFoldableMemAccess()Jonas Paulsson
2017-08-01[Hexagon] Convert HVX vector constants of i1 to i8Krzysztof Parzyszek
2017-07-24[Hexagon] Recognize C4_cmpneqi, C4_cmpltei and C4_cmplteui in NewValueJumpKrzysztof Parzyszek
2017-07-21[Hexagon] Add inline-asm constraint 'a' for modifier register classKrzysztof Parzyszek
2017-07-19[Hexagon] Fix a bug in r308502: post-inc offset is always 0Krzysztof Parzyszek
2017-07-18[Hexagon] Emit lookup tables in text section based on a flagSumanth Gundapaneni
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