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path: root/test/CodeGen/AMDGPU/llvm.dbg.value.ll
AgeCommit message (Expand)Author
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih
2017-12-05AMDGPU: Fix infinite loop with dbg_valueMatt Arsenault
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih
2017-04-07[AMDGPU] Move SiShrinkInstruction and SDWAPeephole to SSAOptimization passesSam Kolton
2017-04-06[AMDGPU] Resubmit SDWA peephole: enable by defaultSam Kolton
2017-04-05Revert r299536. [AMDGPU] SDWA peephole: enable by default.Ivan Krasin
2017-04-05[AMDGPU] SDWA peephole: enable by defaultSam Kolton
2017-03-21AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault
2016-11-29AMDGPU: Disallow exec as SMEM instruction operandMatt Arsenault
2016-07-11AMDGPU: Remove superfluous string attributes from testsMatt Arsenault
2016-04-15[PR27284] Reverse the ownership between DICompileUnit and DISubprogram.Adrian Prantl
2016-04-01testcase gardening: update the emissionKind enum to the new syntax. (NFC)Adrian Prantl
2015-12-22 AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang
2015-12-22Revert "AMDGPU/SI: Use flat for global load/store when targeting HSA"Rafael Espindola
2015-12-22AMDGPU/SI: Use flat for global load/store when targeting HSAChangpeng Fang
2015-11-30AMDGPU: Rework how private buffer passed for HSAMatt Arsenault
2015-11-17Use TargetRegisterInfo for printing MachineOperand register commentsDan Gohman
2015-11-05DI: Reverse direction of subprogram -> function edge.Peter Collingbourne
2015-08-28DI: Require subprogram definitions to be distinctDuncan P. N. Exon Smith
2015-08-12AMDGPU: Fix assert on dbg_value instructionsMatt Arsenault
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