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AgeCommit message (Expand)Author
2018-11-30[XGeneSched] Fixed multiple InstRWllvm_70-amp-20181130release_70-e8af9b4c407-amp-20181130Martin Elshuber
2018-11-30Added XGene modelMartin Elshuber
2018-11-30Merging r339260:Tom Stellard
2018-11-16Merging r344591:Tom Stellard
2018-11-16Merging r344516:Tom Stellard
2018-11-13Merging r342946:Tom Stellard
2018-11-13Merging r342884:Tom Stellard
2018-11-13Merging r341919:Tom Stellard
2018-11-13Merging r341221:Tom Stellard
2018-11-13Merging r340932:Tom Stellard
2018-11-13Merging r340931:Tom Stellard
2018-11-13Merging r340927:Tom Stellard
2018-10-19Merging r343373:Tom Stellard
2018-10-19Merging r343428:Tom Stellard
2018-10-19Merging r343443:Tom Stellard
2018-09-10Merging r341642:Hans Wennborg
2018-09-06Merging r341512:Hans Wennborg
2018-09-04Merging r340959:Hans Wennborg
2018-08-30Merging r340417:Hans Wennborg
2018-08-30Merging r340416:Hans Wennborg
2018-08-30Merging r340455:Hans Wennborg
2018-08-21Merging r340158:Hans Wennborg
2018-08-21Merging r339895 and r339896:Hans Wennborg
2018-08-17Merging r339945:Hans Wennborg
2018-08-16Merging r339769:Hans Wennborg
2018-08-09Merging r339316:Hans Wennborg
2018-08-08Merging r339190:Hans Wennborg
2018-08-07Merging r338610:Hans Wennborg
2018-08-07Merging r338569:Hans Wennborg
2018-08-03Merging r338599:Hans Wennborg
2018-08-02Merging r338554:Hans Wennborg
2018-08-02Merging r338658:Hans Wennborg
2018-08-01[X86] Use isNullConstant helper. NFCI.Simon Pilgrim
2018-08-01[AMDGPU] Optimize _L image intrinsic to _LZ when lod is zeroRyan Taylor
2018-08-01[SystemZ, TableGen] Fix shift count handlingUlrich Weigand
2018-08-01[X86] Use isNullConstant helper. NFCI.Simon Pilgrim
2018-08-01[X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko
2018-08-01[MIPS GlobalISel] Select global addressPetar Jovanovic
2018-08-01Revert "Enrich inline messages", tests failDavid Bolvansky
2018-08-01Enrich inline messagesDavid Bolvansky
2018-08-01[AArch64] Disallow the MachO specific .loh directive for windowsMartin Storsjo
2018-08-01[X86] When looking for (CMOV C-1, (ADD (CTTZ X), C), (X != 0)) -> (ADD (CMOV ...Craig Topper
2018-08-01[x86] Fix a really subtle miscompile due to a somewhat glaring bug inChandler Carruth
2018-08-01AMDGPU: Add clamp bit to dot intrinsicsKonstantin Zhuravlyov
2018-07-31Revert r338354 "[ARM] Revert r337821"Reid Kleckner
2018-07-31[SystemZ] Fix bad assert composition.Jonas Paulsson
2018-07-31AMDGPU: Break 64-bit arguments into 32-bit piecesMatt Arsenault
2018-07-31AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on callsMatt Arsenault
2018-07-31AMDGPU: Scalarize vector argument types to callsMatt Arsenault
2018-07-31[X86] WriteBSWAP sched classes are reg-reg only.Simon Pilgrim
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