summaryrefslogtreecommitdiff
path: root/lib/Target/RISCV
AgeCommit message (Expand)Author
2018-07-26[RISCV] Add support for _interrupt attributeAna Pazos
2018-06-27[RISCV] Add machine function pass to merge base + offsetSameer AbuAsal
2018-06-21[RISCV] Tail calls don't need to save return addressSameer AbuAsal
2018-06-20[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.wAlex Bradbury
2018-06-20[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}Alex Bradbury
2018-06-20[RISCV] Add InstAlias definitions for sgt and sgtuAlex Bradbury
2018-06-13[RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury
2018-06-13[RISCV] Codegen support for atomic operations on RV32IAlex Bradbury
2018-06-08[RISCV] Implement MC layer support for the fence.tso instructionAlex Bradbury
2018-06-07[RISCV] AsmParser support for the li pseudo instructionAlex Bradbury
2018-06-06Fix compilation of WebAssembly and RISCV after r334078Ilya Biryukov
2018-06-01Set ADDE/ADDC/SUBE/SUBC to expand by defaultAmaury Sechet
2018-05-30[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo tableShiva Chen
2018-05-29[RISCV] Add peepholes for Global Address lowering patternsSameer AbuAsal
2018-05-24[RISCV] Support linker relax function call from auipc and jalr to jalShiva Chen
2018-05-23[RISCV] Lower the tail pseudoinstructionMandeep Singh Grang
2018-05-23[RISCV] Set CostPerUse for registersSameer AbuAsal
2018-05-23[RISCV] Add symbol diff relocation support for RISC-VAlex Bradbury
2018-05-23[RISCV] Correctly report sizes for builtin fixupsAlex Bradbury
2018-05-21MC: Separate creating a generic object writer from creating a target object w...Peter Collingbourne
2018-05-21MC: Change MCAsmBackend::writeNopData() to take a raw_ostream instead of an M...Peter Collingbourne
2018-05-18Support: Simplify endian stream interface. NFCI.Peter Collingbourne
2018-05-18[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvancedShiva Chen
2018-05-17[RISCV] Separate base from offset in lowerGlobalAddressSameer AbuAsal
2018-05-17[RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang
2018-05-17[RISCV] Set isReMaterializable on ADDI and LUI instructionsAlex Bradbury
2018-05-17[RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury
2018-05-15[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxa...Shiva Chen
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen
2018-05-11[RISCV] Support .option rvc and norvc assembler directivesAlex Bradbury
2018-05-05Fix a bunch of places where operator-> was used directly on the return from d...Craig Topper
2018-04-26[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlotAlex Bradbury
2018-04-26[RISCV] Implement isZextFreeAlex Bradbury
2018-04-26[RISCV] Implement isTruncateFreeAlex Bradbury
2018-04-26[RISCV] Implement isLegalICmpImmediateAlex Bradbury
2018-04-26[RISCV] Implement isLegalAddImmediateAlex Bradbury
2018-04-26[RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury
2018-04-25[RISCV] Allow call pseudoinstruction to be used to call a function name that ...Alex Bradbury
2018-04-25[RISCV] Expand function call to "call" pseudoinstructionShiva Chen
2018-04-25[RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen
2018-04-18[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury
2018-04-18Revert "[RISCV] implement li pseudo instruction"Alex Bradbury
2018-04-17[RISCV] implement li pseudo instructionAlex Bradbury
2018-04-16[RISCV] Fix assert message operatorMandeep Singh Grang
2018-04-12[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0Sameer AbuAsal
2018-04-12[RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen
2018-04-12[RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury
2018-04-12[RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury
2018-04-12[RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury
2018-04-12[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 09:53:58 +0000