| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-12-07 | [RISCV] MC layer support for load/store instructions of the C (compressed) ex... | Alex Bradbury |
| 2017-12-07 | [RISCV] MC layer support for the standard RV64I instructions | Alex Bradbury |
| 2017-12-07 | [RISCV] MC layer support for the standard RV32F instruction set extension | Alex Bradbury |
| 2017-11-09 | [RISCV] MC layer support for the standard RV32A instruction set extension | Alex Bradbury |
| 2017-10-19 | [RISCV] Prepare for the use of variable-sized register classes | Alex Bradbury |
| 2017-09-28 | [RISCV] Add common fixups and relocations | Alex Bradbury |
| 2017-09-17 | [RISCV] Add support for disassembly | Alex Bradbury |
| 2017-02-14 | [RISCV] Pseudo instructions are isCodeGenOnly, have blank asmstr | Alex Bradbury |
| 2016-11-01 | [RISCV 4/10] Add basic RISCV{InstrFormats,InstrInfo,RegisterInfo,}.td | Alex Bradbury |
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index : ampere-computing/llvm.git | |
| LLVM including Ampere Computing toolchain specific patches |
| summaryrefslogtreecommitdiff |