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path: root/lib/Target/AMDGPU/SIISelLowering.cpp
AgeCommit message (Expand)Author
2017-07-26TargetLowering: Change isShuffleMaskLegal's mask argument type to ArrayRef<in...Zvi Rackover
2017-07-21[SystemZ, LoopStrengthReduce]Jonas Paulsson
2017-07-18AMDGPU: Figure out private memory regs after loweringMatt Arsenault
2017-07-15AMDGPU: Return correct type during argument loweringMatt Arsenault
2017-07-13[AMDGPU] fcaninicalize optimization for GFX9+Stanislav Mekhanoshin
2017-07-12[AMDGPU] fcanonicalize elimination optimizationStanislav Mekhanoshin
2017-07-10Add DAG argument to canMergeStoresTo NFC.Nirav Dave
2017-07-08[AMDGPU] Fix -Wimplicit-fallthrough warning. NFCI.Simon Pilgrim
2017-07-06[AMDGPU] Always use rcp + mul with fast mathStanislav Mekhanoshin
2017-07-06[Constants] If we already have a ConstantInt*, prefer to use isZero/isOne/isM...Craig Topper
2017-06-27[AMDGPU] Simplify setcc (sext from i1 b), -1|0, ccStanislav Mekhanoshin
2017-06-27[AMDGPU] Combine and x, (sext cc from i1) => select cc, x, 0Stanislav Mekhanoshin
2017-06-26AMDGPU: Whitespace fixesMatt Arsenault
2017-06-26AMDGPU: Partially fix implicit.buffer.ptr intrinsic handlingMatt Arsenault
2017-06-22[AMDGPU] Add intrinsics for tbuffer load and store - build error fixDavid Stuttard
2017-06-22[AMDGPU] Add intrinsics for tbuffer load and storeDavid Stuttard
2017-06-21[AMDGPU] Add FP_CLASS to the add/setcc combineStanislav Mekhanoshin
2017-06-21[AMDGPU] Combine add and adde, sub and subeStanislav Mekhanoshin
2017-06-21[AMDGPU] simplify add x, *ext (setcc) => addc|subb x, 0, setccStanislav Mekhanoshin
2017-06-19AMDGPU: Cleanup CreateLiveInRegisterMatt Arsenault
2017-06-12AMDGPU: Teach isLegalAddressingMode about flat offsetsMatt Arsenault
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth
2017-06-06[llvm] Remove double semicolonsMandeep Singh Grang
2017-06-02AMDGPUAnnotateUniformValue should always treat volatile loads as divergentAlexander Timofeev
2017-05-24[AMDGPU] Prevent too large store merges in AMDGPU Subtargets. NFCI.Nirav Dave
2017-05-23[AMDGPU] Combine and (srl) into shl (bfe)Stanislav Mekhanoshin
2017-05-17AMDGPU: Start defining a calling conventionMatt Arsenault
2017-05-17AMDGPU: Make better use of op_sel with high componentsMatt Arsenault
2017-05-17AMDGPU: Fix min3/max3 combines for f16/i16Matt Arsenault
2017-05-11[AMDGPU] Placate unused variable warning in release builds.Davide Italiano
2017-05-11AMDGPU: Pull fneg out of extract_vector_eltMatt Arsenault
2017-05-04AMDGPU: GFX9 GS and HS shaders always have the scratch wave offset in SGPR5Marek Olsak
2017-05-01Generalize the specialized flag-carrying SDNodes by moving flags into SDNode.Amara Emerson
2017-04-28AMDGPU: Add new amdgcn.init.exec intrinsicsMarek Olsak
2017-04-28[SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDem...Craig Topper
2017-04-24Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek
2017-04-24AMDGPU: Move trap lowering to DAGMatt Arsenault
2017-04-21AMDGPU: Do not lower fast unsafe div for safe, f32, with fp32 denormalsKonstantin Zhuravlyov
2017-04-21[AArch64] Improve code generation for logical instructions takingAkira Hatanaka
2017-04-21Revert r300932 and r300930.Akira Hatanaka
2017-04-21[AArch64] Improve code generation for logical instructions takingAkira Hatanaka
2017-04-19AMDGPU: Custom lower illegal small select typesMatt Arsenault
2017-04-12AMDGPU: Fix invalid copies when copying i1 to phys regMatt Arsenault
2017-04-11AMDGPU: Refactor SIMachineFunctionInfo slightlyMatt Arsenault
2017-04-11AMDGPU: Refactor argument loweringMatt Arsenault
2017-04-06AMDGPU/GFX9: Fix shared and private aperture queriesKonstantin Zhuravlyov
2017-04-06AMDGPU: Replace fp16SrcZerosHighBits with a whitelistMatt Arsenault
2017-04-06AMDGPU: Stop using CCAssignToRegWithShadowMatt Arsenault
2017-04-06[AMDGPU] Eliminate barrier if workgroup size is not greater than wavefront sizeStanislav Mekhanoshin
2017-04-04AMDGPU: Remove legacy export intrinsicMatt Arsenault