[llvm-mca] Improve a few debug prints. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337003 91177308-0d34-0410-b5e6-96231b3b80d8

6 files changed, 24 insertions, 22 deletions

diff --git a/tools/llvm-mca/DispatchStage.cpp b/tools/llvm-mca/DispatchStage.cpp
index ad10fbe73e8..be6f1f89be5 100644
--- a/tools/llvm-mca/DispatchStage.cpp
+++ b/tools/llvm-mca/DispatchStage.cpp
@@ -29,7 +29,7 @@ namespace mca {
 
 void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
                                                 ArrayRef<unsigned> UsedRegs) {
-  LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
+  LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n');
   notifyEvent<HWInstructionEvent>(HWInstructionDispatchedEvent(IR, UsedRegs));
 }
 
@@ -73,8 +73,6 @@ void DispatchStage::updateRAWDependencies(ReadState &RS,
 
   collectWrites(DependentWrites, RS.getRegisterID());
   RS.setDependentWrites(DependentWrites.size());
-  LLVM_DEBUG(dbgs() << "Found " << DependentWrites.size()
-                    << " dependent writes\n");
   // We know that this read depends on all the writes in DependentWrites.
   // For each write, check if we have ReadAdvance information, and use it
   // to figure out in how many cycles this read becomes available.
diff --git a/tools/llvm-mca/ExecuteStage.cpp b/tools/llvm-mca/ExecuteStage.cpp
index 40957c26695..437f864b072 100644
--- a/tools/llvm-mca/ExecuteStage.cpp
+++ b/tools/llvm-mca/ExecuteStage.cpp
@@ -135,7 +135,7 @@ bool ExecuteStage::execute(InstRef &IR) {
   if (!HWS.issueImmediately(IR))
     return true;
 
-  LLVM_DEBUG(dbgs() << "[SCHEDULER] Instruction " << IR
+  LLVM_DEBUG(dbgs() << "[SCHEDULER] Instruction #" << IR
                     << " issued immediately\n");
 
   // Issue IR.  The resources for this issuance will be placed in 'Used.'
@@ -153,14 +153,14 @@ bool ExecuteStage::execute(InstRef &IR) {
 
 void ExecuteStage::notifyInstructionExecuted(const InstRef &IR) {
   HWS.onInstructionExecuted(IR);
-  LLVM_DEBUG(dbgs() << "[E] Instruction Executed: " << IR << '\n');
+  LLVM_DEBUG(dbgs() << "[E] Instruction Executed: #" << IR << '\n');
   notifyEvent<HWInstructionEvent>(
       HWInstructionEvent(HWInstructionEvent::Executed, IR));
   RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
 }
 
 void ExecuteStage::notifyInstructionReady(const InstRef &IR) {
-  LLVM_DEBUG(dbgs() << "[E] Instruction Ready: " << IR << '\n');
+  LLVM_DEBUG(dbgs() << "[E] Instruction Ready: #" << IR << '\n');
   notifyEvent<HWInstructionEvent>(
       HWInstructionEvent(HWInstructionEvent::Ready, IR));
 }
@@ -175,11 +175,11 @@ void ExecuteStage::notifyResourceAvailable(const ResourceRef &RR) {
 void ExecuteStage::notifyInstructionIssued(
     const InstRef &IR, ArrayRef<std::pair<ResourceRef, double>> Used) {
   LLVM_DEBUG({
-    dbgs() << "[E] Instruction Issued: " << IR << '\n';
+    dbgs() << "[E] Instruction Issued: #" << IR << '\n';
     for (const std::pair<ResourceRef, unsigned> &Resource : Used) {
       dbgs() << "[E] Resource Used: [" << Resource.first.first << '.'
-             << Resource.first.second << "]\n";
-      dbgs() << "           cycles: " << Resource.second << '\n';
+             << Resource.first.second << "], ";
+      dbgs() << "cycles: " << Resource.second << '\n';
     }
   });
   notifyEvent<HWInstructionEvent>(HWInstructionIssuedEvent(IR, Used));
diff --git a/tools/llvm-mca/InstrBuilder.cpp b/tools/llvm-mca/InstrBuilder.cpp
index c0b25f783c8..dbd457196f9 100644
--- a/tools/llvm-mca/InstrBuilder.cpp
+++ b/tools/llvm-mca/InstrBuilder.cpp
@@ -208,7 +208,8 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
     }
     Write.IsOptionalDef = false;
     LLVM_DEBUG({
-      dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", Latency=" << Write.Latency
+      dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
+             << ", Latency=" << Write.Latency
              << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
     });
     CurrentDef++;
@@ -239,10 +240,12 @@ void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
 
     Write.IsOptionalDef = false;
     assert(Write.RegisterID != 0 && "Expected a valid phys register!");
-    LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", PhysReg="
-                      << Write.RegisterID << ", Latency=" << Write.Latency
-                      << ", WriteResourceID=" << Write.SClassOrWriteResourceID
-                      << '\n');
+    LLVM_DEBUG({
+      dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
+             << ", PhysReg=" << MRI.getName(Write.RegisterID)
+             << ", Latency=" << Write.Latency
+             << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
+    });
   }
 
   if (MCDesc.hasOptionalDef()) {
@@ -297,7 +300,8 @@ void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
     Read.OpIndex = i + CurrentUse;
     Read.UseIndex = CurrentUse;
     Read.SchedClassID = SchedClassID;
-    LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex);
+    LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex
+                      << ", UseIndex=" << Read.UseIndex << '\n');
   }
 
   for (unsigned CurrentUse = 0; CurrentUse < NumImplicitUses; ++CurrentUse) {
@@ -306,8 +310,8 @@ void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
     Read.UseIndex = NumExplicitUses + CurrentUse;
     Read.RegisterID = MCDesc.getImplicitUses()[CurrentUse];
     Read.SchedClassID = SchedClassID;
-    LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex
-                      << ", RegisterID=" << Read.RegisterID << '\n');
+    LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex << ", RegisterID="
+                      << MRI.getName(Read.RegisterID) << '\n');
   }
 }
 
diff --git a/tools/llvm-mca/RegisterFile.cpp b/tools/llvm-mca/RegisterFile.cpp
index 502807e0857..63fe0d2d72e 100644
--- a/tools/llvm-mca/RegisterFile.cpp
+++ b/tools/llvm-mca/RegisterFile.cpp
@@ -213,7 +213,7 @@ void RegisterFile::collectWrites(SmallVectorImpl<WriteRef> &Writes,
   LLVM_DEBUG({
     for (const WriteRef &WR : Writes) {
       const WriteState &WS = *WR.getWriteState();
-      dbgs() << "Found a dependent use of Register "
+      dbgs() << "[PRF] Found a dependent use of Register "
              << MRI.getName(WS.getRegisterID()) << " (defined by intruction #"
              << WR.getSourceIndex() << ")\n";
     }
diff --git a/tools/llvm-mca/RetireStage.cpp b/tools/llvm-mca/RetireStage.cpp
index a708c982cd3..386ec54d7ba 100644
--- a/tools/llvm-mca/RetireStage.cpp
+++ b/tools/llvm-mca/RetireStage.cpp
@@ -43,7 +43,7 @@ void RetireStage::cycleStart() {
 }
 
 void RetireStage::notifyInstructionRetired(const InstRef &IR) {
-  LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
+  LLVM_DEBUG(dbgs() << "[E] Instruction Retired: #" << IR << '\n');
   SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
 
diff --git a/tools/llvm-mca/Scheduler.cpp b/tools/llvm-mca/Scheduler.cpp
index a2561fc3582..975a50e4b63 100644
--- a/tools/llvm-mca/Scheduler.cpp
+++ b/tools/llvm-mca/Scheduler.cpp
@@ -363,7 +363,7 @@ void Scheduler::updateIssuedQueue(SmallVectorImpl<InstRef> &Executed) {
       ++I;
       IssuedQueue.erase(ToRemove);
     } else {
-      LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction " << Entry.first
+      LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << Entry.first
                         << " is still executing.\n");
       ++I;
     }
@@ -382,7 +382,7 @@ bool Scheduler::reserveResources(InstRef &IR) {
   // If necessary, reserve queue entries in the load-store unit (LSU).
   const bool Reserved = LSU->reserve(IR);
   if (!IR.getInstruction()->isReady() || (Reserved && !LSU->isReady(IR))) {
-    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding " << IR << " to the Wait Queue\n");
+    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the Wait Queue\n");
     WaitQueue[IR.getSourceIndex()] = IR.getInstruction();
     return false;
   }
@@ -392,7 +392,7 @@ bool Scheduler::reserveResources(InstRef &IR) {
 bool Scheduler::issueImmediately(InstRef &IR) {
   const InstrDesc &Desc = IR.getInstruction()->getDesc();
   if (!Desc.isZeroLatency() && !Resources->mustIssueImmediately(Desc)) {
-    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding " << IR
+    LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR
                       << " to the Ready Queue\n");
     ReadyQueue[IR.getSourceIndex()] = IR.getInstruction();
     return false;