MIR: Print the register class or bank in vreg defs

This updates the MIRPrinter to include the regclass when printing
virtual register defs, which is already valid syntax for the
parser. That is, given 64 bit %0 and %1 in a "gpr" regbank,

  %1(s64) = COPY %0(s64)

would now be written as

  %1:gpr(s64) = COPY %0(s64)

While this change alone introduces a bit of redundancy with the
registers block, it allows us to update the tests to be more concise
and understandable and brings us closer to being able to remove the
registers block completely.

Note: We generally only print the class in defs, but there is one
exception. If there are uses without any defs whatsoever, we'll print
the class on all uses. I'm not completely convinced this comes up in
meaningful machine IR, but for now the MIRParser and MachineVerifier
both accept that kind of stuff, so we don't want to have a situation
where we can print something we can't parse.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316479 91177308-0d34-0410-b5e6-96231b3b80d8

9 files changed, 20 insertions, 25 deletions

diff --git a/test/CodeGen/Hexagon/cext-opt-basic.mir b/test/CodeGen/Hexagon/cext-opt-basic.mir
index 5ad44c1e3ea..63530c88c1e 100644
--- a/test/CodeGen/Hexagon/cext-opt-basic.mir
+++ b/test/CodeGen/Hexagon/cext-opt-basic.mir
@@ -8,7 +8,7 @@
 ...
 
 # CHECK-LABEL: name: test0
-# CHECK: [[B:%[0-9]+]] = A2_tfrsi @global_address
+# CHECK: [[B:%[0-9]+]]:intregs = A2_tfrsi @global_address
 # CHECK: L2_loadri_io [[B]], 0
 # CHECK: L2_loadri_io [[B]], 4
 # CHECK: L2_loadri_io [[B]], 8
@@ -26,8 +26,8 @@ body: |
 ...
 
 # CHECK-LABEL: name: test1
-# CHECK: [[C:%[0-9]+]] = COPY %r0
-# CHECK: [[B:%[0-9]+]] = A2_addi [[C]], @global_address
+# CHECK: [[C:%[0-9]+]]:intregs = COPY %r0
+# CHECK: [[B:%[0-9]+]]:intregs = A2_addi [[C]], @global_address
 # CHECK: L2_loadri_io [[B]], 0
 # CHECK: L2_loadri_io [[B]], 4
 # CHECK: L2_loadri_io [[B]], 8
@@ -48,11 +48,11 @@ body: |
 ...
 
 # CHECK-LABEL: name: test2
-# CHECK: [[C:%[0-9]+]] = COPY %r0
-# CHECK: [[B:%[0-9]+]] = A2_tfrsi @global_address + 4
-# CHECK: [[T0:%[0-9]+]] = A2_addi [[B]], -4
+# CHECK: [[C:%[0-9]+]]:intregs = COPY %r0
+# CHECK: [[B:%[0-9]+]]:intregs = A2_tfrsi @global_address + 4
+# CHECK: [[T0:%[0-9]+]]:intregs = A2_addi [[B]], -4
 # CHECK: %r0 = COPY [[T0]]
-# CHECK: [[T1:%[0-9]+]] = A2_addi [[B]], -2
+# CHECK: [[T1:%[0-9]+]]:intregs = A2_addi [[B]], -2
 # CHECK: %r1 = COPY [[T1]]
 # CHECK: L4_loadri_rr [[B]], [[C]], 0
 ---
@@ -72,4 +72,3 @@ body: |
     %r1 = COPY %2
     %3 = L4_loadri_ur %0, 0, @global_address+4
 ...
-
diff --git a/test/CodeGen/Hexagon/early-if-debug.mir b/test/CodeGen/Hexagon/early-if-debug.mir
index 39b5036f810..7c8fb0aee10 100644
--- a/test/CodeGen/Hexagon/early-if-debug.mir
+++ b/test/CodeGen/Hexagon/early-if-debug.mir
@@ -3,16 +3,16 @@
 # if-converted.
 
 # CHECK-LABEL: bb.0:
-# CHECK: %0 = COPY %r0
-# CHECK: %1 = C2_cmpeqi %0, 0
-# CHECK: %2 = A2_tfrsi 123
+# CHECK: %0:intregs = COPY %r0
+# CHECK: %1:predregs = C2_cmpeqi %0, 0
+# CHECK: %2:intregs = A2_tfrsi 123
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
 # CHECK: DBG_VALUE debug-use %0, debug-use _
-# CHECK: %3 = A2_tfrsi 321
-# CHECK: %5 = C2_mux %1, %2, %3
+# CHECK: %3:intregs = A2_tfrsi 321
+# CHECK: %5:intregs = C2_mux %1, %2, %3
 
 --- |
   define void @foo() {
diff --git a/test/CodeGen/Hexagon/expand-condsets-def-undef.mir b/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
index 44da969bf29..702099a4453 100644
--- a/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-def-undef.mir
@@ -32,10 +32,9 @@ body: |
     %1 = COPY %r0
     %2 = COPY %d0
     ; Check that this instruction is unchanged (remains unpredicated)
-    ; CHECK: %3 = A2_addi %2.isub_hi, 1
+    ; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
     %3 = A2_addi %2.isub_hi, 1
     undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
     %2.isub_hi = C2_muxir %0, %3, 0
 
 ...
-
diff --git a/test/CodeGen/Hexagon/expand-condsets-imm.mir b/test/CodeGen/Hexagon/expand-condsets-imm.mir
index 1b0988393b7..141db645329 100644
--- a/test/CodeGen/Hexagon/expand-condsets-imm.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-imm.mir
@@ -1,6 +1,6 @@
 # RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
 # Check that we can expand a mux with a global as an immediate operand.
-# CHECK: C2_cmoveif undef %0, @G
+# CHECK: C2_cmoveif undef %0:predregs, @G
 
 --- |
   @G = global i32 0, align 4
@@ -19,4 +19,3 @@ body: |
     %1 = C2_muxir undef %0, %1, @G
     %r0 = COPY %1
 ...
-
diff --git a/test/CodeGen/Hexagon/expand-condsets-impuse.mir b/test/CodeGen/Hexagon/expand-condsets-impuse.mir
index 08b6798aa2f..725e414f521 100644
--- a/test/CodeGen/Hexagon/expand-condsets-impuse.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-impuse.mir
@@ -53,7 +53,7 @@ body: |
         %7 = L2_loadrb_io %99, 12
         %8 = C2_cmpeqi %7, 9
         %9 = A2_tfrsi -999
-        ; CHECK: %10 = C2_cmoveit killed %8, -999, implicit %10
+        ; CHECK: %10:intregs = C2_cmoveit killed %8, -999, implicit %10
         %10 = C2_mux %8, %9, %1
         J2_jumpr %10, implicit-def %pc
 
diff --git a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
index f3d105f75da..e4c54c4b988 100644
--- a/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
+++ b/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
@@ -39,8 +39,8 @@ body: |
         %1 = COPY %r1
         %2 = COPY %p0
         ; Check that %3 was coalesced into %4.
-        ; CHECK: %4 = A2_abs %1
-        ; CHECK: %4 = A2_tfrt killed %2, killed %0, implicit %4
+        ; CHECK: %4:intregs = A2_abs %1
+        ; CHECK: %4:intregs = A2_tfrt killed %2, killed %0, implicit %4
         %3 = A2_abs %1
         %4 = C2_mux %2, %0, %3
         %r0 = COPY %4
diff --git a/test/CodeGen/Hexagon/hwloop-redef-imm.mir b/test/CodeGen/Hexagon/hwloop-redef-imm.mir
index d1bb1efb651..014908e20a7 100644
--- a/test/CodeGen/Hexagon/hwloop-redef-imm.mir
+++ b/test/CodeGen/Hexagon/hwloop-redef-imm.mir
@@ -7,7 +7,7 @@
 # possible and legal (since the immediate itself will be used in the
 # loop setup in the preheader).
 
-# CHECK:  [[R0:%[0-9]+]] = A2_tfrsi 1920
+# CHECK:  [[R0:%[0-9]+]]:intregs = A2_tfrsi 1920
 # CHECK:  J2_loop0r %bb.1.b1, [[R0]]
 #
 # CHECK: bb.1.b1 (address-taken):
diff --git a/test/CodeGen/Hexagon/regalloc-liveout-undef.mir b/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
index 6a41514b060..a6a398f0cdf 100644
--- a/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
+++ b/test/CodeGen/Hexagon/regalloc-liveout-undef.mir
@@ -6,7 +6,7 @@
 # cover live intervals as well.
 #
 # Make sure that this compiles successfully.
-# CHECK: undef %1.isub_lo = A2_addi %1.isub_lo, 1
+# CHECK: undef %1.isub_lo:doubleregs = A2_addi %1.isub_lo, 1
 
 ---
 name: fred
@@ -32,4 +32,3 @@ body: |
         undef %1.isub_lo = A2_addi %1.isub_lo, 1
         J2_jump %bb.1, implicit-def %pc
 ...
-
diff --git a/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir b/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
index 6d6549201ab..a8c342f296c 100644
--- a/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
+++ b/test/CodeGen/Hexagon/unreachable-mbb-phi-subreg.mir
@@ -17,9 +17,8 @@ body: |
 
   bb.2:
     ; Make sure that the subregister from the PHI operand is preserved.
-    ; CHECK: %[[REG:[0-9]+]] = COPY %0.isub_lo
+    ; CHECK: %[[REG:[0-9]+]]:intregs = COPY %0.isub_lo
     ; CHECK: %r0 = COPY %[[REG]]
     %1 : intregs = PHI %0.isub_lo, %bb.0, %0.isub_hi, %bb.1
     %r0 = COPY %1
 ...
-